Hello Brian,
The DS90CF384A's output can only strobe on the falling edge. There are a couple devices that have a user-selectable clock edge:
24-bit, 5-35MHz: DS90C124
18, 24, or 30-bit, 8-135MHz: DS90C3202
Thanks,
Kate
Other Parts Discussed in Thread: DS90C3202 , DS90C3201 , DS90C387A Dear Sirs
About DS90C3202: 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver 1. Dual TTL Out R/G/B (10/10/10=totaling 60 bits) port Mode: ? MHz max.(CLKOUT) Single TTL Out R/G/B (10/10/10=totaling…
Other Parts Discussed in Thread: DS90C3202 Hi all
There are the following questions in "Absolute Maximum Ratings" table of DS90C3202 data sheet. 1. "Package Derating" What is meant? 2. Although theta(ja) is not indicated, what value…
Other Parts Discussed in Thread: SN75LVDS83A , DS90C3202
In one of our design, we have two boards (VMC board & UI board). Both are connected through a ribbon cable of 1' and 1m length.
VMC board has iMX283 processor with 24bit RGB interface connected…
Hello,
Unfortunately there may not be a solution with the same footprint as the DS90CR218A, however take a look at this device:
DS90C3202 - 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
Regards,
Ben Dattilo
Hello Danny,
Can you please check DS90C3202? This device can support 9MHz PCLK and has similar functionality.
http://www.ti.com/lit/ds/symlink/ds90c3202.pdf
Best Regards,
Casey
Hi Lacey,
1. Yes
2. They need to use the SPI CLK as the input clock for the SN65LVDS93A if the frequency is 100MHz.
3. Shielded Cat -5/-6/-7 should be fine.
4. Yes. However, if they're now certain that the frequency is 100MHz then they can consider the…
Hi Julian,
Thanks for the background information and the additional waveforms. I presume these waveforms have been taken right at the input of the DS90C3202?
This type of common mode noise is dangerously beyond the allowable Vcm range specified by the…
