Part Number: DS90UH941AS-Q1 Hi Expert,
I have some question about internal/external pixel clock and video timing.
As you can see below for 941 0x65 reg, my understanding is that if I use internal video timing, I can choose internal or external pixel…
Part Number: DS90UH941AS-Q1 Hi team,
I have a question about the register related to Port1 when I configure the device as Single DSI input, Dual FPD-Link output.
It is described that BCC is only available for primary (Port 0?) in this configuration, but…
Part Number: DS90UH941AS-Q1 Hi team,
In Dual Link mode, can I use D_GPIO as either input or output of DS90UH941AS-Q1?
Or the direction of D_GPIO is only DES to SER?
Could you advise how to configure below GPIO_1 amd GPIO_2_Config Register (0xE) [6:4]…
Part Number: DS90UH941AS-Q1 Hello,
I want to connect DS90UH941&DS90UH948, and make D-GPIOs pass through.
Please check whether it can work in the two figures.
Part Number: DS90UH941AS-Q1 Hi Team,
We used external DSI and find the CNTRL_ERR_HSRQST ERROR = '1'. Can you let me know the meaning and which point may be the root cause?
Roy
Part Number: DS90UH941AS-Q1 Hi team,
Could you advise the purpose of the BCC watchdog timer (0x16) in UH941?
I would also would like to know how it works(what does it monitor?)?
regards,
Part Number: DS90UH941AS-Q1 Hi Team,
If the 941AS is being used in single lane mode on DOUT0+/-, is it okay to leave AC coupling caps and the CMC on DOUT1+/-?
Thanks,
Jared
Part Number: DS90UH941AS-Q1 Hi Team,
When using an external oscillator or crystal to generate the 941AS clock, does the frequency of the oscillator/crystal need to match the target display PCLK exactly? Or are there any M/N dividers that can be used from…
Part Number: DS90UH941AS-Q1 Other Parts Discussed in Thread: ALP Hi Team,
Our setup is 941+984 with external dual DSI and CLK. Our DSI clk is 92MHz*2 = 184MHz. But the ALP shows the 200MHz. I'm not sure if this is the deviation? In addition, can you…
