Part Number: DS90UH947-Q1 Hi Team,
How can we calculate the estimated delay time for GPIO mapping. (Both of FC and BC)
Condition :
FPD3 single lane
PCLK : 50MHz
Backward channel : 20Mbps
Regards,
Roy
Part Number: DS90UH947-Q1 Dear Specialists,
My customer is interested in FPD Link3 for Fiber cable transmission.
According to the related thread, without using backchannels, It is stated that it can be used if the specifications of the serializer and deserializer…
Part Number: DS90UH947-Q1 Hello,
My setup is currently
LVDS->947->948->display
Meanwhile, I have I2C devices connected to the 948 I2C bus that I am trying to access using a microcontroller that is connected to the I2C bus on the 947.
I am changing…
Part Number: DS90UH947-Q1 Hi team,
In order to improve EMC performance, I would like to add 2200pF in addition to 10nF default value.
Is there a side effect to decrease pefromance or reliability of the device?
#20 LF pin
#63 LFOLDI pin
regards,
Hey Roy,
Roy Chou1 said: 948 didn't send DE signal
Can you also check the lock signal while DE signal is lost ? Is this DE signal loss happening in conjunction with loss of lock?
Regards, Fadi A.
Part Number: DS90UH947-Q1 Hi team,
Could you advise if there is a proper power down sequence for VDD11 and VDD18?
In my case, VDD18 start to drop before VDD11 completely go down to 0V.
In my understanding, as far as the device power up with proper sequence…
Part Number: DS90UH947-Q1 Hi,TI
The address of 948 is the same,will there be a conflict by configuring the 948 through the same I2C?
The slave devices can configure slave ID and slave alias to avoid conflict issues.
The configuration of the 948 conflicts…
Hi Logan,
Yes, they met the sequence. Do you have any update in your side?
Logan Cummins said: Can you verify if customer is inputting OLDI data before release of PDB as per the recommended startup sequence?
Regards,
Roy