Part Number: DS92LV8028 What if the parallel data in is asynchronous for DS92LV8028? Does it matter if the clock edge is on the data edge every once in awhile? Metastability? What do I do about it when the LVDS is interfaced to an FPGA.
Hi Cem,
Sorry for the delay and thanks for the clarification. This will be a bit difficult and rather complicated to implement with what we have.
One idea:
Serializer: DS92LV3221: This Channel Link II serializer will serialize up to 32 parallel inputs…