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  • TI-JESD204-IP: Where is terms of use

    Part Number: TI-JESD204-IP Tool/software: Hi team, Is there terms of use for using TI-JESD204-IP? I would like to check whether it can be provided to a third party for maintenance. Regards, Hiromu

  • TI-JESD204-IP: JESD IP support for Intel Altera FPGAs

    TI Thinks Resolved
    Part Number: TI-JESD204-IP Tool/software: Hi, Found the following thread: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1306209/ti-jesd204-ip-about-altera-jesd-ip-cores?tisearch=e2e-sitesearch&keymatch=TI-JESD204…
    • Answered

  • TI-JESD204-IP: TI-JESD204 for Xilinx z7030 part Vivado loopback error

    Resolved
    Part Number: TI-JESD204-IP Tool/software: Dear all, we are starting TI-JESD204-IP (1.11) evaluation with Vivado 2019.2 simulator. The simulation of zc706 unmodified example works fine, using the loopback, we can see data sent to be also received. Then…
    • Resolved
    • Answered

  • TI-JESD204-IP: JESD204C IP Core Integration Issue in Vivado for ZC706

    Resolved
    Part Number: TI-JESD204-IP Tool/software: Hi All, There is a bit of problem when trying to add the JESD204C IP core (TI_204c_IP) on the current version of Vivado 2023.1 for the ZC706 board. I've added the IP to my design, but I'm getting the following…
    • Resolved
    • Answered

  • RE: TI-JESD204-IP: zcu102_8b10b IP works fine for 8 lanes but gives rx_lane_invalid_eomf_err_count

    Resolved
    One more observation is that the sys_clk should have frequency as LineRate/80 ( for datawidth of 64). So according to LineRate sys_clk should also change along with ref_clk. During simulations, we tend to miss out this much needed change.
    • Answered

  • RE: TI-JESD204-IP: Two ADCs (ADS52J900) to be connected to single JESD Instantiation in FPGA

    Resolved
    Hi Amit, Thanks for the clarification and suggestion. Yes we plan to use external ref_clk and sysref source. Thanks, Trushal
    • Answered

  • RE: TI-JESD204-IP: ADS52J90 K value =3 for 4 lane mode JESD IP does not work

    Resolved
    Hi Ameet, Thanks for the keen support. This helped. Regards, Trushal

  • TI-JESD204-IP: Please reply to my email.

    TI Thinks Resolved
    Part Number: TI-JESD204-IP Tool/software: I received a request email 3 weeks ago. I immediately wrote the specs I wanted in an excel file and sent them. And I waited for JESD204 IP for more than 3 weeks. I still haven't received a reply. When can I expect…

  • RE: TI-JESD204-IP: Abnormal program termination (EXCEPTION_ACCESS_VIOLATION) when synthesizing in Vivado 2024.1

    Disable incremental synthesis in the vivado project settings. That should do it. Did you manage to simulate it properly in vivado 2024? I'm getting a bunch of "end of multiframe" errors in simulation..

  • RE: TI-JESD204-IP: Project Error Using Vivado 2024.1

    Hi Erivelton, Using the TI_204c_IP.svp file is required in order for the project to work. Using only the '_entity.sv' file will not work as this file will only have the ports used by the .svp file and should not be imported to the design. I…

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