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  • ADS1675: Clock Jitter/SNR Relational Graph

    TI Thinks Resolved
    Part Number: ADS1675 Good afternoon, We're looking at using the ADS1675 for our design but could not find a specification in the datasheet that shows the relationship between clock jitter tolerance and SNR. Are there additional resources that show this…
    • Answered

  • ADS4225: CLKOUT Jitter and SNR

    Resolved
    Part Number: ADS4225 Hi teams, I have questions about ADS4225 jitter. I guess the clock jitter from CLKOUT is calculated from aperture jitter 140 fs. It results in 1 / (140 * 77.7MHz) =92ps where fs is 77.7MHz. And it also equals t_jitter. Is…
    • Resolved
    • Answered

  • [FAQ] The relationship between SNR and ADC clock jitter

    Resolved
    Hi team, Why the clock jitter will affect the SNR of ADC? How to get the following equation?
    • Resolved
    • Answered

  • ADC12DJ3200QML-SP: SNR and clock jitter used in datasheet

    Resolved
    Part Number: ADC12DJ3200QML-SP Hi Team, We have a customer inquiry regarding figure 28 on page 29 of ADC12DJ3200QML-SP datasheet. 1. SNR is dependent on clock jitter. These are the measured results. 2. Do you know what the clock jitter is in these measurements…
    • Resolved

  • ADS131M04: Do you have any graph which shows relation between CLKIN jitter and SNR?

    TI Thinks Resolved
    Part Number: ADS131M04 Hello guys, One of my customers is considering using ADS131M04 for their new products. They want to use MSP430 clock output (8MHz) as ADS131M04 CLKIN. But the clockoutput has about +/-3% jitter. So they want to know how much…
    • Answered

  • ADS5294: Jitter vs. SNR

    Resolved
    Part Number: ADS5294 Other Parts Discussed in Thread: LMK04826 I am aware of the relationship between sample clock jitter and SNR. If I am using a clock generator device, what I am unclear about is which of the jitter specifications I should be using…
    • Resolved

  • PCM1794A: Jitter requirements / impact on SNR

    TI Thinks Resolved
    Part Number: PCM1794A What is the max jitter specification required on SCK3 in order to meet the specified SNR (say -125dB @ 17kHz)? For example, with a 48kHZ sample clock (SCLK3 = 18.432MHz, 384Fs) and an output frequency we calculate the jitter needed…
    • Answered

  • ADS42LB69 - SNR versus Input Frequency and External Clock Jitter

    Resolved
    Other Parts Discussed in Thread: ADS42LB69 Hello, In the datasheet of ADS42LB69 , there is the Figure 22 SNR versus Input Frequency and External Clock Jitter. And there the 5 curves which have jitter from 35fs~200fs. <Question 1> Is this Figure calculated…
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    • Answered

  • DB83640 PHY and LaunchPAD rating(Excellent,Fair,Poor) for Jitter and Receiver SNR values

    Resolved
    Other Parts Discussed in Thread: DP83640T-EVK Using the Analog LaunchPAD application and DP83640T-EVK (Ethernet phy with USB access). Select the tab Cable and Jitter (Variance) and Receiver SNR values are reported with a rating Excellent, Fair, Poor etc…
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    • Answered

  • RE: ADC3441: Input clock jitter tradeoffs

    Resolved
    Hi Ben, The clock jitter, ideally, will not impact the spurious performance of the ADC, so SFDR should remain stable, but SNR will primarily impacted. This figure on page 51 is showing the effects of the ADC aperture jitter on increasing input frequencies…

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