Hi Sadaf,
Unfortunately, we do not offer an mbed library or mbed framework for our CC2564x devices. We only offer Bluetooth stacks for MSP432, STM32, and Linux devices.
You should still be able to use HCI commands to communicate with the device over…
Hi Schuyler:
Sorry, I re-test the TI EVM, the below is the full ETH0/ETH1 log.
The red line log will let the user confuse.
It seems the log is not matching the ETH status consistence.
So, I need to assign the address to let the ETH0 activate to…
Part Number: TDA4VM
Hi there,
We are bringing up multiple cameras running on SDK 8.5, on both CSI0 and CSI1 of TDA4VM.
We are using the DS90UB960 to feed multiple FPDLink cameras (using DS90UB953) into a single CSI input, and we are using both CSI0…
Part Number: BQ76905 Tool/software: Dear TI Expert,
Please refer to attached datasheet. BQ76905_prelim_datasheet.pdf
Can TI supply this IC as standalone?
Can you provide updated datasheet if it is at full scale?
It has One-time Programmable…
Hello George,
Thanks for your replay.
Regarding the second warning test case:
Compiler version: TI v16.9.6.LTS [TI v18.1.1.LTS]
Build output:
**** Build of configuration Debug for project AutosarCanStack ****
"C:\\ti\\ccsv8\\utils\\bin\\gmake…
Thanks George,
compiler version: TI v16.9.6.LTS [TI v18.1.1.LTS]
Here is the build console output:
**** Build of configuration Debug for project AutosarCanStack ****
"C:\\ti\\ccsv8\\utils\\bin\\gmake" -k -j 8 arch/arm-cortexM4/drivers/Can.obj…
Luiz,
this peripheral cannot sync to other parts of the device like the eCAP.
The result is a 32bit value, since its called a Q16 the user is meant to assume that it is a 16 bit interger and a 16 bit fractional portion. After reading this wiki article…
Part Number: TMS320C6678 Other Parts Discussed in Thread: TMS320TCI6616 This document describes how to configure memory protection for catching SW issues on TMS320C66x (KeyStone) devices.
Memory protection on KeyStone devices is implemented in a distributed…
You might try adding #pragma top of functions suspected to being overrun by CPU speed. The CCS simulator & emulator do slow code execution down quite a (bits) no pun intended. Assuming you have CLA section defined for code relocation into SRAM, you might…
