Part Number: MSP430FR6879 Tool/software: Hi
I think SPI data pin status after communication (not driving by eUSCI peripheral) is defined PxREN & PxOUT register.
(referenced : https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers…
Part Number: MSP430FR6989 Other Parts Discussed in Thread: MSP430FR6879 Hi,
what`s the main difference between the two? ´Can the MSP430FR6879 used as a drop-in replacement for the MSP430FR6989?
Thanks!
Hi, Bruce
Bruce McKenney said: result of features described in the User Guide.
Is the description of UG you are talking about the following NOTE? I thought this NOTE contained the nuance that "may cause" does not always occur.
Bruce McKenney…
Part Number: MSP430FR6879 Other Parts Discussed in Thread: MSP-FET
Hi,
Please teach me about the RST pin of MSP430FR6879.
When RST pin is pulling up with an external 47kΩ to use MSP-FET, can the internal pullup of the RST pin is enabled or disabled …
Part Number: MSP430FR6879 Hi,
Is there any information on the internal pull-up value of the RST pin (such as internal pull-up at 47kΩ ± 20%)?
Thanks,
Koki
Part Number: MSP430FR6879
Hi,
The following NOTE is described in the user's guide.
(U ser's guide 12.2.6 Port Interrupts https://www.tij.co.jp/jp/lit/ug/slau367p/slau367p.pdf )
For example, P1.0 is the input port and P1.1 is the output port.
①…
Part Number: MSP430FR6879 Hi experts,
The following questions about TimerA and DMA could not be confirmed from the document, so I would appreciate it if you could tell me about them.
[TimerA] The time chart for the capture mode with SCS=1 is shown in …
Part Number: MSP430FR6879 Other Parts Discussed in Thread: MSP-FET
Hi,
Question1
The document stated that "BOR resets when the change in power supply voltage is ± 0.05 V / μs or more."
Does the BOR reset due to a sudden power rise…
Part Number: MSP430FR6879 Hi,
(1) Are the RAM values after BOR, POR, and PUC indefinite or retained, respectively?
(2) If value of RAM is indefinite after reset , is it also indefinite when Vcore is on ?
I asked this question because I thought the RAM value…
Hi, LI
Is it correct to understand that with the default settings of MPU, the compiler automatically assigns program code to segment 3?
Xiaodong LI said: CPU can check Segmentation Border 2 and Border 1 on 9.7.3 MPUSEGB2 Register and 9.7.4 MPUSEGB1 Register…