Part Number: RM48L940 Tool/software: Hello jagadish,
I am interested in Hercules Microcontrollers, which is SIL2/3 complains.
We are working on the Railway project.
we are using Embedded C+ FreeRTOS.
Other requirements are,
Flash size 4MB (minimum…
Part Number: RM48L940 Tool/software: Hi Team, we are working on SIL2/3 based projects. We are yet to finalize the controller and software(mostly looking for SAFERTOS and RM48L940 ) your product suits as per our requirement. Drivers using:CAN,I2C,SPI,UART…
Part Number: RM48L940 Other Parts Discussed in Thread: HALCOGEN How do I configure the non-multiplexed DMM port pins as GPIO?
e.g. DMM_CLK, DMM_DATA0
I don't see a gioPORT_t definition for DMM to enable me to use a construct similar to how SPI or…
Part Number: RM48L940 We have planned to use RM48L940 Hercules Processor in our design. As per the datasheet it is given that "The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronous DRAM…
Part Number: RM48L940 I am interested to know what are the PLL clock settings done in the development board. I want mainly the register settings for the following fields
For PLL1
1. NR
2. NF
3. OD
4. R
For PLL2
1. NR2
2. NF2
3. OD2 …
Part Number: RM48L940 Same question as here:
https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/585578?TMS570LS0332-Regarding-register-read-back-feature-of-L2L3-configuration-registers
and here
https://e2e.ti.com/support/microcontrollers…
Part Number: RM48L940 When I attempt to read ESM Grp 3 status register (address 0xFFFFF520) I get garbage content from RAM (stack location). I'm able to read Grp 1 and Grp 2 status registers as well as other registers from the ESM module without a problem…
Part Number: RM48L940 When I run the clock monitor test, the Clock Fail status register is never set so my test waits infinite at the while((systemREG1->GBLSTAT & 0x1U) == 0U). The PLL Slip test works fine. What can I check to determine and resolve what…
Part Number: RM48L940 My 1Bit ECC Flash test seems to pass, but it fails 2Bit ECC test using SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_2BIT, 0, &failInfoFla sh) . In the code segment below the, the condition (BIT(ESM_G3ERR_FMC_UNCORR) == (sl_esmREG->SR1[2…
Part Number: RM48L940 For peripherals like MIBSPI and CAN that are configured for use as GPIO, what is the appropriate safety diagnostics to run? Is any of the RAM test necessary for peripherals when they are configured and used as GPIO?
What kind of…
