Part Number: SN65DP159 Other Parts Discussed in Thread: TUSB3410 Hi,
How can I access I2C register for SN65DP159 via TUSB3410 bridge?
I think there is a firmware to burn in a EEPROM connected TUSB3410, right?
Could you please send me firmware for DP159…
Part Number: SN65DP159 Other Parts Discussed in Thread: TMDS181 HI Ti TEAM:
We want to use SN65DP159 at the HDMI 2.0 RX side to replace TMDS181.(We want to remove TMDS181)
HDMI CONN(HDMI 2.0 RX) ---> SN65DP159--> Xilinx FPGA --> (XILINX HDMI IP)…
Part Number: SN65DP159 Other Parts Discussed in Thread: TDP142 , TDP2004 Hi
Could you help suggest RETIMER or REDRIVER as products for Intel's new platform ARROW LAKE,
The display in the product will have DP++ (expected to support HBR3 speed, 4 LANES…
Part Number: SN65DP159 Tool/software: Dear Specialists,
My customer is considering SN65DP159 and has a question.
I would be grateful if you could advise.
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Regarding SN65DP159,
DatasheetP.20 9.3.2 Operation Timing There are two regulations listed below…
Part Number: SN65DP159 Hi Forum,
I am making this thread as a verification that I have routing pins 38 and 39 correctly on the SN65DP159RSBR IC. These pins are the SCL and SDA lines for interfacing with DP source. While updating the CCA that uses this…
Part Number: SN65DP159 My design uses an SN65DP159RSBR to interface with a SMARC standard SBC card. On the DP side, the following signals are passed to the CPU on the SBC.
1. DP0+/- (Pins 6,7)
2. DP1+/- (Pins4,5)
3. DP2+/- (Pins1,2)
4. DP3+/- (Pins9,10)
5.…
Part Number: SN65DP159 Hellow.
I want to convert Dispalyport (v1.2) output through xilinx's zynq device to an HDMI signal.
I am wondering if I can use SN65DP159 as shown below to convert to HDMI.
Zynq's Displayport version is 1.2a and only uses…
Part Number: SN65DP159 I'm using the DDC level shifter features of the SN65DP159, however the SCL_SRC pin appears to be broken:
The DDC_CLK signal idles at 0.5V when connected to SN65DP159 SCL_SRC. When disconnected from SCL_SRC, it idles 3.3V.
…
Part Number: SN65DP159 We are building a video device where the source of the output signal is an Altera FPGA. The problem is out put on the 4 N channels is flat - meaning it is not the inverse of the corresponding P. Pins are 21 OUT_CLKN 22 OUT_CLKP 24 O…