Other Parts Discussed in Thread: SN65LVCP114 , TFP410 , HD3SS215 , TMDS442 Hi,
I have designed a PCB, using SN65LVCP114 to mux DVI signal, and it works well with PC output.
But there is one equipment with chip TFP410 to output DVI signal.
TFP410 OUTPUT,…
Other Parts Discussed in Thread: SN65LVCP114 Hello Team,
Can you leave open the three level control input pin of SN65LVCp114 to set to Hi-Z ?
I believe the answer is YES because the device is internally biasing to mid level of VCC. However looking at the…
Other Parts Discussed in Thread: SN65LVCP114 Hello Team,
Please allow me to ask you a few questions about I2C_SEL and CS pin for SN65LVCP114.
[Q1] When using in I2C mode, when do you use CS pin=Low ? I believe it should be kept high.
[Q2] When using in…
Other Parts Discussed in Thread: SN65LVCP114 Hi Team,
I see the description of "AGC loop" in the SN65LVCP114 datasheet register map. User could set AGC loop Enable/Disable through I2C. However, there were no detail description about this AGC loop.…
Hi Francisco,
We have confirmed the registers settings and the data path are correct. We are still trying to get the equipments to get the eye diagrams.
However, I was browsing Ti's forum and ran across the topic SN65lvcp114 SFI interface. Michael…
Hi,
There are I2C registers which can switch the output polarity. See the registers 0x10 and 0x11 in the datasheet.
If layout is easier to swap both the SFP+ and PHY (P/N) connections as indicated there is no issue. The SN65LVCP114 does not recognize…
Hello,
I have a question and review of below block and your recommend.
Application : XG-PON and OLT Switch MUX operation.
System boards 10G-KR and connected using MUX.
Question is connection AOUT & BOUT and available A or B system recovery time is under…
Other Parts Discussed in Thread: SN65LVCP114 Please help answer the following questions on the SN65LVCP114
1. By default on 10G SFI line, do I have to enable squelched or not? “ “FST_SW” line to high?
2. For controlling this device between…
Other Parts Discussed in Thread: SN65LVCP114 Hi,
Our customer is considering VCC(2.5V/3.3V) supplied devices for SN65LVCP114 . Are there any constraints ?
・Supply Noise, power voltage ripple
・rise time and fall time(10% to 90%)
・output current changes(A/us…
Hi E2E,
I'd like to loop the output port AOUTP/N to BINP/N with an FPGA output driving AINP/N. AOUTP has a +1.3dB gain into BINP/N.
This is a basic loopback test, and Fig. 13 of the datasheet would indicate that this is safe. Are there any gotchas…
