Hello Annie,
If you mean the loading the SN65LVDT386 presents on its input to whatever is driving it, then it is 5 pF (input capacitance of SN65LVDT386 in the datasheet). If this is not what you are asking for, please explain what you are asking for…
Other Parts Discussed in Thread: SN65LVDT386 , SN65LVDS386 Hello,
I have a question concerning the SN65LVDT386.
In the data sheet I can read: Maximum recommended signalling rate 250Mbps (=125MHz?). On page 9 of the data sheet I can see plots up to…
Hello Nanjunda,
All LVDS receivers, if fully compliant to the LVDS standard should support any input voltage level between 0V and 2.4V on its input terminals. In your application scenario, the maximum input voltage level will result when the FPGA transmits…
Other Parts Discussed in Thread: SN74LVCH16T245 , SN65LVDS116 , SN65LVDT386 Hello,
I would like to find out if this deign would work. I have a 90MHz LVDS signal that I would like to fanout and drive 50 ohm lines at ~ 5V CMOS level. My proposed solution…
Hello Mike,
Thank you very much for your answer.
I am going to use SN65LVDT386 to convert two 8-bit parallel buses on up to 297MHz clock frequency.
For the sampling clock signal SN65LVDT2D used.
Both parallel buses and the clock are coming from…
