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Showing 14 results View by: Thread Post Sort by
  • SN74AUP1G79: Low power d-flip flip

    Han Wang
    Han Wang
    TI Thinks Resolved
    Part Number: SN74AUP1G79 Tool/software: Hi expert, Do we have a d-type flip flop that consume even less power than SN74AUP1G79? Thanks Han
    • 7 months ago
    • Logic
    • Logic forum
  • SN74AUP1G79: SN74AUP1G74 SN74AUP1G79 SN74AUP1G80 pspice models

    Paulo Monteiro
    Paulo Monteiro
    TI Thinks Resolved
    Part Number: SN74AUP1G79 Other Parts Discussed in Thread: SN74AUP1G74 , , TINA-TI , SN74AUP1G80 I need the SN74AUP1G74 SN74AUP1G79 SN74AUP1G80 pspice models for TINA-TI simulation. Can someone send me these models? Thanks.
    • over 3 years ago
    • Logic
    • Logic forum
  • Answered
  • RE: SN74AUP1G74: ibis model

    Owen Westfall
    Owen Westfall
    Resolved
    Hi Steve, We do not have one for this part, but typically IBIS files are used to support Input / Output models. If that is the case the SN74AUP1G79 has an identical IO structure just missing the PRE, and CLR inputs would this work for you? Regards, Owen …
    • 2 months ago
    • Logic
    • Logic forum
  • SN74AUP1G79: SN74AUP1G79

    Christa Smeets
    Christa Smeets
    TI Thinks Resolved
    Part Number: SN74AUP1G79 Hello, We have several partnumbers ended with G4 for example: SN74AUP1G79DCKTG4 On the website I only find the following partnumber: SN74AUP1G79DCKT to order. could you please explane why there is nof G4 at the end? Regards, …
    • over 6 years ago
    • Logic
    • Logic forum
  • Answered
  • SN74AUP1G79: How to use this part on downclocking application? 5kHz to 2.5kHz.

    daniel
    daniel
    Resolved
    Part Number: SN74AUP1G79 Other Parts Discussed in Thread: SN74AUP1G80 , Hi Team, How to use this part on downclocking application. 5kHz to 2.5kHz? 5kHz input to pinD? How to set CLK signal? Thanks
    • Resolved
    • over 7 years ago
    • Logic
    • Logic forum
  • Answered
  • RE: SN74AUP1G79 power up state

    Emrys Maier
    Emrys Maier
    Resolved
    Hi Krzysztof, As Ryan stated above, the output of the device is unknown at power-up. Only after a valid clock pulse has been detected will the output state be defined.
    • over 8 years ago
    • Logic
    • Logic forum
  • D FlipFlop Startup state? sn74aup1g79 and sn74aup1g80

    Giraffey
    Giraffey
    TI Thinks Resolved
    Hello I am trying to understand the output state on the AUP D flip flops when VCC is applied. Thanks!
    • over 8 years ago
    • Logic
    • Logic forum
  • CDCLVC1104 and SN74AUP1G79 latch up?

    Jordan Fine
    Jordan Fine
    Hi, I have a lvcmos clock buffer driving an D-Flip flop, and lvcmos buffer listed above. Once the boards came back assembled the clock line signal was attenuated and offset. At first I thought the oscillator was bad, but after pulling off the oscillator…
    • over 10 years ago
    • Logic
    • Logic forum
  • Answered
  • RE: SN74LVC1G373: What is high-impedance state for?

    Clemens Ladisch
    Clemens Ladisch
    Resolved
    When the OE input is high, the Q output is in the high-impedance state (driven neither high nor low). This is probably not what you want, so keep OE low. For the latch, to change the output, LE must be high. To keep the old state, LE must be low. So you…
    • over 5 years ago
    • Logic
    • Logic forum
  • RE: About SN74AUP1G17-EP

    Sheng Wang
    Sheng Wang
    Other Parts Discussed in Thread: SN74AUP1G74 , SN74AUP1G79 , SN74AUP1G17 Hold on please, Shreyas, I took a looks on both SN74AUP1G79 and SN74AUP1G74 (bot are clocked devices !), but their "Fclock" has a huge difference. see page 6 of 1G74 and page7 of 1G79…
    • over 9 years ago
    • Space & High Reliability (Read Only)
    • Space & High Reliability Forum (Read Only)
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