Part Number: SN74AUP1G79 Other Parts Discussed in Thread: SN74AUP1G74 , , TINA-TI , SN74AUP1G80 I need the SN74AUP1G74 SN74AUP1G79 SN74AUP1G80 pspice models for TINA-TI simulation.
Can someone send me these models? Thanks.
Part Number: SN74AUP1G79 Hello,
We have several partnumbers ended with G4 for example: SN74AUP1G79DCKTG4
On the website I only find the following partnumber: SN74AUP1G79DCKT to order.
could you please explane why there is nof G4 at the end?
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Part Number: SN74AUP1G79 Other Parts Discussed in Thread: SN74AUP1G80 , Hi Team,
How to use this part on downclocking application. 5kHz to 2.5kHz?
5kHz input to pinD?
How to set CLK signal?
Thanks
Hi Krzysztof,
As Ryan stated above, the output of the device is unknown at power-up. Only after a valid clock pulse has been detected will the output state be defined.
to add to the conversation and link to an app note on clocked devices :
www.ti.com/.../scha005a.pdf
To have a set output , consider using AUP1G74 and have the preset or clr enabled .
Hi Ryan,
The clk is going into the clk input of the flip flop.
I removed the buffer and replaced the flip-flop with a new one and everything works. Before not only was my buffer stuck at high, but my FPGA was acting strange, i.e. the counter I had…
Hi Steve,
We do not have one for this part, but typically IBIS files are used to support Input / Output models. If that is the case the SN74AUP1G79 has an identical IO structure just missing the PRE, and CLR inputs would this work for you?
Regards…
When the OE input is high, the Q output is in the high-impedance state (driven neither high nor low). This is probably not what you want, so keep OE low.
For the latch, to change the output, LE must be high. To keep the old state, LE must be low. So…
Other Parts Discussed in Thread: SN74AUP1G74 , SN74AUP1G79 , SN74AUP1G17 Hold on please, Shreyas,
I took a looks on both SN74AUP1G79 and SN74AUP1G74 (bot are clocked devices !), but their "Fclock" has a huge difference. see page 6 of 1G74 and page7…
