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  yang yang2

  • 11 months ago
  • Logic
  • Logic forum

  SN74AUP1G80: The initial logical level of Q output of SN74AUP1G80

  • Resolved

  Part Number: SN74AUP1G80 Hi, TI experts Q output feed back to D pin through a 10K resistor
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  Karan Kotadia

  • over 2 years ago
  • Logic
  • Logic forum

  RE: TINA/Spice/SN74AUP1G80: Need the SPICE Model

  Hello Kumar, So we don't currently have a spice model for this part however, since you needed something urgently, I made the following for you. It is very similar to the behavior of the AUP1G80 however it may not behave perfectly. SN74AUP1G80_Behavioral_Model_v180828...
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  Jerry Chu

  • over 2 years ago
  • Logic
  • Logic forum

  SN74AUP1G80: VCC=1V, VIH=?

  • Resolved

  Part Number: SN74AUP1G80 Hi Expert, If the VCC=1V, what's the VIH minimum value? Thanks!
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  Chuchen Wang

  • over 2 years ago
  • Logic
  • Logic forum

  SN74AUP1G80: Timing Question

  • Resolved

  Part Number: SN74AUP1G80 Hi, My customer is interested in using this SN74AUP1G80 as a clock divider
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  Alpha H

  • over 1 year ago
  • Power management
  • Power management forum

  RE: TPS22933: Add / mux a second output

  Hey Chris, Welcome back! I can answer some of your questions regarding the TPS22933, and I'll loop in a member from our logic team to comment on the SN74AUP1G80. The TPS22933 has B2B FETs between VOUT and the 3 inputs, so the output will be protected...
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  Ryan Andrews

  • over 4 years ago
  • Logic
  • Logic forum

  SN74AUP1G80 Output Rise Time

  TI Thinks Resolved

  Hello, I'm using the SN74AUP1G80 as a clock divider and was wondering how to determine the expected output rise/fall times. My CLK input is a 16MHz LVCMOS clock signal operating at either 1.8V or 3.3V. Right now I'm measuring ~10ns rise times...
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  Gabriel Lake1

  • over 1 year ago
  • Logic
  • Logic forum

  RE: SN74AUP1G74: Application review

  Hello, It looks like this will work fine, however since the preset and clear pins on the flip flop are not necessary here, you might consider the SN74AUP1G80 which only needs 5 pins and would save a little space. Also since you are not using the voltage...
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  Emrys Maier

  • over 2 years ago
  • Logic
  • Logic forum

  RE: SN74AUP1G79: How to use this part on downclocking application? 5kHz to 2.5kHz.

  Hi Daniel, The SN74AUP1G79 is not ideal to use as a clock divider since it does not have an inverted output. I would recommend using the SN74AUP1G80 instead. If you are set on using the 1G79, just add an inverter after Q to get Q\ and use the diagram...
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  ShreyasRao

  • over 4 years ago
  • Logic
  • Logic forum

  RE: D FlipFlop Startup state? sn74aup1g79 and sn74aup1g80

  to add to the conversation and link to an app note on clocked devices : www.ti.com/.../scha005a.pdf To have a set output , consider using AUP1G74 and have the preset or clr enabled .
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  Ryan May

  • over 5 years ago
  • Logic
  • Logic forum

  SN74AUP1G79 power up state

  • Resolved

  Hello, I am working with the SN74AUP1G79 / SN74AUP1G80 . I need to know that if I have CLK and D

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