If you want to redrive a 165 MHz clock (ie a 330 Mbps data stream), and 27 other similarly fast digital signals at 3.3V, there's not a lot of options in the standard logic portfolio.
The two options I found would be the SN74AVC16827 (20 bit buffer…
Hi Vijay,
1. Please find the fft plot below with 0V differential input signal.
2. The input to differential signal is a 3.4Vpp sine wave at 16MHz. Please find the update plot below. As shown, a lot of spurs are present in the Nyquist band. These…
ALB,
Is your EVM a Rev C board? If so I have attached the schematic. Please make sure all jumpers are set per the board photo I am sending. Take a scope probe (diff probe would be better) and monitor the ADC input across R21 and R26. You should see…
Jin,
The schematic looks good for the most part. Please do the following:
1. Install R364 to provide a path to GND.
2. Do not use R361, R362, and R363 wit the ADC_VCM output.
3. Make sure DRVDD and AVDD are 3.3V.
4. Do not need to route ADC_CLKOUTM_F…
Hello Jim,
Apologies for the late reply. I have been traveling and have now just starting to catch up to all the E2E questions.
The revision C of the schematic is attached. The major change on this revision is that we have replaced U15 from a 16-bit…
