• SN74LVC1G175: 74LVC1G175DCKRG4 P2P device

  

  Bonnie Chen

  TI Thinks Resolved

  Part Number: SN74LVC1G175 Other Parts Discussed in Thread: SN74LVC1G374 , SN74LVC1G80 Hi Team, do you have 74LVC1G175DCKRG4 P2P device but with below condition? Pin4 Q = Not gate chip? 74LVC1G175DCKRG4, Power on default Pin4_Q is open drain?

  • over 5 years ago
  • Logic
  • Logic forum
Answered

• RE: SN74LVC1G126: Problem: The simulation results of thi-state gate are not correct, the result about high resistance state are same with an AND gate.

  

  Nu Pu

  Resolved

  OK, the problem has been found and hope I can download the updated PSPICE file on the official product page soon. Please do not forget that the PSPICE model of SN74LVC1G125 has the same problem, which needs to be corrected. SN74LVC1Gxxx series of logic…

  • over 4 years ago
  • Logic
  • Logic forum
Answered

• Output state of D-flip flop

  

  Keerthika Subramanian

  Resolved

  Other Parts Discussed in Thread: SN74LVC1G374 I am using the TI device SN74LVC1G374. Regarding it, I have a doubt about its output state during power up. In this configuration for the D-Flip flop, the clock signal is given by Shut down_TTL. It is held…

  • Resolved

  • over 10 years ago
  • Logic
  • Logic forum

• Initial output of a D-Flipflop?

  

  Martin Fuchs

  Other Parts Discussed in Thread: SN74LVC1G374 Hello! Is the initial output Q (Hi/Lo) after power-up of the SN74LVC1G374 predictable? I could not find this info in the datasheet. (Of course, I read the part of pulling the /OE up for a safe power-up. But…

  • over 13 years ago
  • Logic
  • Logic forum

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