Part Number: SN74LVC2G32 Hi E2E,
Good day!
May I know what is the correct pinout for the YZP package of SN74LVC2G32. The pinout on page 3 is not in BGA pin numbering so it is quite confusing. Also, after checking the ultralibrarian file, the pinout is…
Part Number: SN74LVC2G32-EP Hi, Greetings. Our customer is looking for the rated junction temperature of SN74LVC2G32-EP however it is not available on the datasheet. We would appreciate if you could provide us this information. Looking forward to your response…
Part Number: SN74LVC2G32-Q1 Hi TI-team
I have a question.
Does SN74LVC2GXXX have tolerant system ?
I want to use at Input 5V when Vcc is 3.3V.
Best Regards,
Koji Hayashi
Part Number: SN74LVC2G32 Trying to understand Icc vs delta Icc spec. Can you explain with more detail. Is it this:
Icc is the static Iq when inputs are the same logic level
Delta Icc is the static Iq with inputs at different logic levels?
Thx, Andy
Hello Malcolm-san,
I got their reply which states their system requires and show those in the attached. Would you please check the attached and give me your comments and input your suggestion if you have?
CD4027B_Alternatives_2024July12.pptx
Best Regards…
Part Number: SN74LVC2G07 Other Parts Discussed in Thread: SN74LVC2G32 , SN74LVC2G125 , SN74LVC1G97 Hi,
Customers need Dual Buffer with Open-Drain outputs, such as SN74LVC2G07, but with enable function. I only found Dual buffer (3-state output) with enable…
Build a two-bit counter with flip-flops. Reset it on power up or when it reaches the fourth state. Use an OR gate to create the logic-1 output from the 01 or 10 state.
The flip-flop and the AND gate need Schmitt-trigger inputs, so use SN74HCS74 and SN74LVC1G97…
Hi kate, Thank you for your kind support. I understood how to calculate power dissipation of the multiplexer. Please let me ask one more question. How should other logic ICs estimate it? ex) SN74LVC2G32
Rds(ON) is not described for logic devices. If so, how…
Hi Bart,
the simplest analog only way I could come up with is the following block diagram:
Essentially, the Master can switch on/off all communication channels and the Slaves can choose to whom they want to send the signal.
For the multiplexers I would…
With two CD4511Bs, A 1 = NOT 12, B 1 = 3 OR 12, C 1 = 15, D 1 = 9, A 2 = 12 OR 15. So this would need 1× SN74LVC1G14 and 1× SN74LVC2G32.
Without any 7-segment decoders, a = d = g = on, b = 3 OR 9 OR 12, c = NOT 2, e = 2, f = 5 OR 9, b 2 = c 2 = 2…
