Hi,
I am trying to use this D Flip-Flop in an application where a set of push button controls the output state of the chip. I don't need a clock signal, just that the output state be held until the next event state.
The datasheet doesn't make it…
Part Number: SN74LVC2G74-Q1 Hi Team,
My customer wants to know the CDM ESD classification level of SN74LVC2G74-Q1.
Could you help provide it?
Thanks,
Molly
Part Number: SN74LVC2G74-Q1 Hi team,
Our customer is using SN74LVC2G74-Q1 in their design.
There is a capacitive load connectted the output pin and will result a 120mA/70ns pulse to the output pin.
I have not found the parameters related to this in…
Part Number: SN74LVC2G74-Q1 Other Parts Discussed in Thread: SN74HCS74-Q1 Posting on behalf of Balazs Kelenvolgyi:
A customer asked me why the input transition rise or fall rate is defined so short (5nS) in the datasheet of SN74LVC2G74QDCURQ1? They want…
Part Number: SN74LVC2G74-Q1 Hi All,
I have a question about SN74LVC2G74-Q1.
There is CLVC2G74QDCURG4Q1 as shown below. What is the difference from SN74LVC2G74QDCURQ1?
Best Regards, Ishiwata
Part Number: SN74LVC2G74-Q1 Hi team,
What is the outputs when the pin PRE and CLR is H, while CLK is H?
I see other competitor device marked here as non low to high transition and ours marked as L. Are they the same?
Matthew
This is a solution that I found to work for me. Using the sn74lvc2g74-q1 with the data and clock inputs grounded, the set and clear inputs are asynchronous and this does exactly what I want. Simple schematic for reference. Cheers, Charlie
Part Number: SN74LVC2G74-Q1 Other Parts Discussed in Thread: SN74HCS74 Hi
I would like to know what timing does SN74LVC2G74-Q1 sample the high/low level of input ?
in the case below, Vcc, D, and CLR connected to Vcc. The PRE pin connected to Vcc with a…