Hello,
In our board FPGA I/O lines are connected to the inputs of the 245 and the I/O voltage is set to 2.5V. The FPGA is not configured so I presume the interface pins between the FPGA and 245 must be tri-stated. The 245 might either be pulling…
Other Parts Discussed in Thread: SN74LVCH16T245 Dear TI,
I'm using SN74LVCH16T245 for translating 2.8V camera signals to 3.3V camera signals. This IC has embedded with Bus-hold function.
1. Please let us know, how to enable and dis-enable the bus hold…
Other Parts Discussed in Thread: SN74LVCH16T245 DEARS.
Cio of SN74LVCH16T245 is mean?
Product variation is generated during production?
SN74LVCH16T245 variation is a value that can be generated during operation?
It can be changed due to the deterioration…
Other Parts Discussed in Thread: SN74LVC8T245 , SN74LVCH16T245 I need to convert I/O signals between a 5V ASIC and a 3.3V FPGA. I was planning to use the SN74LVC8T245 with VCCA = 3.3V and VCCB = +5V. The ASIC will tristate its I/O signals for lengthy periods…
Other Parts Discussed in Thread: SN74LVCH16T245 , SN74AVCH16T245 , SN74AVC16T245 , TUSB1310A Hello,
I am using SN74LVCH16T245 VOLTAGE LEVEL TRANSLATOR for translating from 3.3V to 1.8V. My data rate is 250 Mbps but I am getting very degraded output. Please…
Other Parts Discussed in Thread: SN74LVCH16T245 what is maximum data rate one can achieve using SN74LVCH16T245? I want to operate it for logic level 3.3V to 5V conversion. In data sheet tPLH and tPHL are specified as 4.4 ns max that means 225 MHz?
Thank you Clemens.
In case of SN74LVCH16T245, to get worst case tpzx, should I add tpxz & tpLH/tpHL (or) I can directly take it from the datasheet's "switching characteristics". Because the summation and the value given as a total tpZX given in datasheet…