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Part Number: SN75LVDS82 Other Parts Discussed in Thread: SN75LVDS83B Hi Team,
My customer use SN75LVDS82 to interface with i.MX8 and has while noise abnormal display issue.
Their original design is:
GPU(AMD LX800)(TTL-DRGB-24bit) -> TI SN75LVDS83B -> …
Part Number: SN75LVDS82 Other Parts Discussed in Thread: DS90CR285 , , SN65LVDS93 HI
I have a board with a channel link receiver DS90CR285 , which is 3V3 interface for FPGA.
I need to use 1V8 FPGA banks.
Can I use SN75LVDS82 (FlatLink) as 1V8 alternative…
Hi Nikolas,
1. DCLK is 25.77MHz from SN75LVDS82 pin 26
2. We managed to solve this problem by setting the output clock from i.mx8mplus to 25MHz.
We didn't notice that before although we set it up as 25MHz but it automatically changed to 75MHz after booting…
Part Number: SN75LVDS82 Please confirm the LVDS input signal of SN75LVDS82DGG. Does the LVDS input support SSC (SpreadSpread Spectrum clock)? If it is supported, please let me know what percentage of down clock it supports.
Best Regards
Part Number: SN75LVDS82 Hi team,
My customer uses SN75LVDS82DGG to design. DVT assembly 15 set but only 2 pcs will have some issues as below.
When we use a heat gun to blow to SN75LVDS82DGG for about 3~5 seconds, the LCD display is normal (no red stripes…
Part Number: SN75LVDS82 Hi team, Can SN75LVDS82 support SXGA? Due to the upper clock frequency limit of 68 MHz on the data sheet, I do not think XSGA can support this. If it can, please let me know how to the setting. If it cannot, please introduce a device…
Part Number: SN75LVDS82 Hi Team,
Good day. Please help with the below concern.
Can unused differential inputs i.e. A3P/A3M be left unconnected?
Thank you for your help.
Kind regards,
Marvin
