Part Number: SN75LVPE5412 Other Parts Discussed in Thread: SN75LVPE5421
May you provide the SN75LVPE5412+SN75LVPE5421 EVM board .dsn file?
We need it to design PCIe X4 Gen5 AIC for MCIO 38P and Gen-Z for reference.
Part Number: SN75LVPE5412 Hi,
According to the presentation, there is no specified AC caps location for chip to chip.
I would like to know whether there is specified length or limitation or placing AC caps at receiver side?
Thanks and Best regards,
Part Number: SN75LVPE5412
Datasheet is mentioned to tie RSVD1 (pin2) and RSVD2 (pin12) to GND for best signal integrity performance.
However, our EVM is tied to 0.1uF cap to GND.
Because PCB space concern, we would like to direct ground these 2…
Part Number: SN75LVPE5412 Hi team,
My customer encountered some questions when they simulate our SN75LVPE5412 IBIS-AMI Model. Could you kindly help me to solve this?
If there are recommended Pre and post side loss distribution when we want to achieve…
Part Number: SN75LVPE5412 Hi Team,
Customer want to use SN75LVPE5412, but the temp range is 0~85 degree only.
Why the temp range is so narrow for a new designed device? Customer need -40 ~ 125.
Part Number: SN75LVPE5412 Other Parts Discussed in Thread: SN75LVPE5421 Hi,
If my customer don't want to use Mux function for SN75LVPE5412/5421, I want to confirm whether they could use both of SN75LVPE5412 or SN75LVPE5421 at RX path just do confirm…
Part Number: SN75LVPE5421 Other Parts Discussed in Thread: SN75LVPE5412 Hello,
I found that TI has MUX SN75LVPE5421 and SN75LVPE5412, the use case is one RP to two EPs(x8 + x8 or x 16 + x0).
If I want to use two RPs to connected to one NVMe EP, and hot…