Part Number: TDA4APE-Q1 Tool/software: Hi TI experts,
We have very strict power requirements to go as low as 1-1.5W in the SoC, however, we still have to keep a DDR active for code and data holding.
The question is, how do we reach the lowest possible…
Part Number: TDA4APE-Q1 Tool/software: Hi Support,
I'm working with TDA4APE HS device. I need your support to unlock jtag port using Trace32 and Lauterbach.
As my reference it seems you provide a cmm package. Can I get it for TDA4APE SoC?
Thanks…
Part Number: TDA4APE-Q1 Tool/software: Hi,
We're using this target derivative: J742S2- TDA4APE
The SoC supports 3 DSPs, 2 of which have MMA units.
My question is, ho do we identify those on the multi-core image level (core IDs), SDK and also the OVX…
Part Number: TDA4VP-Q1 Tool/software: Dear Ti Team,
There is mismatch of height in the thermal model vs the datasheet.
Request you to clarify the same, Let us know if any latest model available.
Regards
Prashanth Kumar G N
Part Number: TDA4AP-Q1 Tool/software: Hello,
from the TDA4 datasheet Table 6-2 there is only one parameter given. Can you please provide more information about: single ended crossing voltage area (min, max) absolute voltage range for p/n signals required…
Hi Brijesh,
Yes, we could close it now, the follow patch makes it work, thanks!
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 8af95e9da7ce..9b64ed738574 100644
--- a/drivers…
Part Number: TDA4AP-Q1 Tool/software: Hi,
We're using this target derivative: J742S2- TDA4APE
I was wondering if you could share the datasheet for this SoC with me.
I need to confirm the target specific features and processors.
Thanks.
Part Number: TDA4AP-Q1 Tool/software: Hi TI Experts,
Customer is working on TDA4AP SDK10.0.
Customer now is developing the communications between cddipc & A72. As you know we need the IPC local endpoint for A72 to do that.
We have followed the below…
Hi Kevin,
It is safer to first check if the DDR is cached in the customer's application.
Kevin Peng said: However, how could they run mcu1-1 in the non-cached region if they still want run into ddr, is it possible to make a part of DDR to cached, and…
