Part Number: TDA4APE-Q1 Other Parts Discussed in Thread: SYSCONFIG Hi experts,
We are developing a board based on TDA4APE-Q1. We plan to use 2 chips of 4GB DRAM of which the brand type is MT53E1G32D2FW-046 AAT:B. We need to confogure the DDR but we…
Part Number: TDA4APE-Q1 Hi experts,
We are developing a custom board based on TDA4APE. And I'm trying to genenrate a square wave with PWM. We are using pin F33, i.e. EHRPWM4_B to generate the wave.
The corresponding dts configs are shown below.
…
Part Number: TDA4APE-Q1 Other Parts Discussed in Thread: SYSCONFIG As discussed with selva@ti.com and prayag.sahoo@ti.com SOC used here: TDA4APE6-Q1 1. SGMII5 TX lines not visible, even though Sysconfig tool is started Fresh, But SGMII 5 tx is available…
Hi,
venkatesan s said: We are developing a custom board for the AI Analytics card using the TDA4APE6-Q1 SoC and require three video outputs from the board:
Understood, you are planning to use 3 video outputs from the SoC.
venkatesan s said: Could…
Hi Shreyas,
ShreyasRao said: Gokul Praveen , Siddharth Vadapalli do you know about the driver code he is referring to?
The code snapshot in the below link is the one he is referring to.
https://e2e.ti.com/support/processors-group/processors/f/processors…
Part Number: TDA4APE-Q1 Other Parts Discussed in Thread: SEGGER Hello experts,
Which debuggers are supported for TDA4APE4 during development?
My understanding is following debuggers are supported. Are there any other debuggers?
What is the difference…
Hi Mian,
Mian DENG said: I've recompiled the spi driver with change shown below, but the problem remains the same. Is there any other possible reason?
While there are no activities on the SPI lines, can you run "k3conf dump device | grep -i spi…
Part Number: TDA4APE-Q1 Hi TI experts,
I'm working on TDA4APE with sdk11.0 to do ISP tunning for a raw12 traffic sensor (OV OG12A sensor). The images of this sensor are combined of HCG and LCG frames, and the PWL in sensor is 16 bit to 12 bit.
However…
Part Number: TDA4APE-Q1 Tool/software: Hey
I have a question about the RMII clock configuration on P379 of the TRM.
The RMII clock configuration consists of Figure 5-23(a) and (b), but the document states that (a) configuration is not supported. …
Hi,
Marinus Holzner said: -In addition, we would be grateful for a brief explanation of the importance of the purple area in the diagram.
It is the approximate location of the "trained" delay and VREF settings.
Marinus Holzner said: -Does the "Diamond…
