Other Parts Discussed in Thread: EK-TM4C1294XL Tool/software: TI-RTOS Dear Support Team,
We have assembled this reference desing, and able to run the benchmarking example code with it. Now I am looking for some help, how can I make this memory managed…
Hi,
The TI Reference design https://www.ti.com/tool/TIDM-TM4C129SDRAMNVM is everything we have. Refer to section 3.2.2 for details.
Below is the software collateral.
TIDM-TM4C129SDRAMNVM.zip
Hi,
Serial NAND Flash memory should follow the industry-standard serial peripheral interface (SPI x1/x2/x4). There is no reason MSP432E cannot support NAND flash.
Here is one TI reference design that uses TM4C129 MCU to interface with serial flash device…
Hi,
Please take a look at this TI Reference Design. https://www.ti.com/tool/TIDM-TM4C129SDRAMNVM . Although this design was for TM4C129 MCU but it is the same silicon as MSP432E. They use the same driverlib. This design should run code out of SDRAM. The…
Part Number: TIDM-TM4C129SDRAMNVM Other Parts Discussed in Thread: EK-TM4C1294XL Hi,
I am trying to purchase the board TIDM-TM4C129SDRAMNVM from the link
www.ti.com/.../TIDM-TM4C129SDRAMNVM
using the Order Now icon. But everytime I do it the EK-TM4C1294XL…
Hi,
In MSP432E SDK, we have a basic SDRAM example that you can find at C:\ti\simplelink_msp432e4_sdk_4_20_00_12\examples\nortos\MSP_EXP432E401Y\driverlib\epi_sdram_basic. I strongly suggest you run this example first on your board to make sure you can…
Hi,
Conor said: Q1 When using EPI0S as an address bus and data bus, is it necessary to process a pull-up resistor, etc.?
Q2
No. That is not necessary.
Conor said: Q2 Is it necessary to process the pins of the memory control lines assuming that they operate…
Part Number: MSP432E401Y Dear Charles Tsai,
I hope this message finds you well. I am writing to report an issue with the MSP432 microcontroller unit, specifically related to booting from the External SDRAM starting address is 0x60000000.
As you recommended…
Hi Naga,
naga narasimha said: 1. After adding pull up resister for CS pin as you suggested and we did not find any changes in SDRAM write and read operations.
2. The Still CS pin is toggling in Ideal state ?
It is possible if the command is just NOP…
