Part Number: TIDM-TM4CFLASHSRAM Tool/software: Hello Team,
We're planning to use TM4C with external memory devices as in TIDM-TM4CFLASHSRAM EVK.
We need to store large number of data which will be transferred in chunks via SPI to an FPGA. As the SRAM…
Part Number: TM4C129XNCZAD Other Parts Discussed in Thread: TIDM-TM4CFLASHSRAM We have a new device designed with a TM4C129xnczad using the TIDM-TM4CFLASHSRAM. We are currently using a 24 BPP raster and having issues with our LCD screen updating at a…
Bump This_Post said: The DoDMA function is reading in data from an external flash using CPU memory, then writing it to an external SRAM using CPU memory, currently I am trying to configure the DMA to do that instead.
Hi,
I think I may have given you…
Part Number: TM4C129XNCZAD Other Parts Discussed in Thread: TIDM-TM4CFLASHSRAM
So we currently have a device that uses a basic 640 x 480 screen with a raster input. The problem is that we are using an external SRAM as the LCD frame buffer, this is updating…
Other Parts Discussed in Thread: TIDM-TM4CFLASHSRAM Hi Team, Our customer would like to request for the design files of the TIDM-TM4CFLASHSRAM reference design. The files are apparently one of the key factors on the processor selection for their new project…
Other Parts Discussed in Thread: TIDM-TM4CFLASHSRAM , TM4C129XNCZAD Need assistance to get Altium and/or Eagle design files for TIDM-TM4CFLASHSRAM and DK-TM4C129X. The links in the documentation http://www.ti.com/tool/TIDM-TM4CFLASHSRAM do not direct…
Hi,
Yes, you can use the EPI to interface with external memories. Please refer to this reference design https://www.ti.com/tool/TIDM-TM4CFLASHSRAM . You can download the software collateral from /cfs-file/__key/communityserver-discussions-components…
Then the TIDM-TM4CFLASHSRAM will be a good start point for you to reference. As mentioned, this example contains a custom bootloader called ektm4c129_epiflash_bootloader (see below) which will copy the example application called ektm4c129_epiflash_boot_demo…
Part Number: MSP432E401Y I'm currently designing a microcontroller board with MSP432E401Y which uses EPI Host bus muxed mode for interfacing with 3 devices(SRAM, Parallel Flash and FPGA)
To segregate the address and data line, should i add a D-latch…
