Part Number: TLV320AIC24K Hello,
I have used four codec (TLV320AIC24K), with one master device and three slave devices since 2006 year.
Then recently it is occurring the issue that the FS(Frame Sync) signal is out of sync on some boards in low temperature…
Part Number: TLV320AIC24K Hi,
We are using three TLV320AIC24KIPFBG4 in cascaded mode in master slave configuration along with an FPGA.
The FPGA configures all three codecs and the first codec in the chain is the master.
The following is the requirement…
Part Number: TLV320AIC24K Other Parts Discussed in Thread: TLV320AIC24 Hi TI,
What is the CHIP ID( Chip version ) for TLV320AIC24 audio codec?
Please let me know how to know the Chip ID.
Regards,
Deepeshwar
Hello,
Thank you for your reply.
Details for the issues without a series resistor are the followings.
1. After SCLK output of the master device disappears in operation, SCLK appears again, and repeats it.
2. In that time, the voltage level of…
Part Number: TLV320AIC24K Hi,
We are using TLV320AIC24K in our design and we are providing 1.8V to core and 3.3V to IOs.
Does this device need any power sequencing?
Regards,
Archana Rao
Part Number: TLV320AIC24K Hi,
We are using three TLV320AIC24KIPFBG4 audio codecs in cascaded mode on our board with microphone input and 150 ohms audio outputs.
We are referencing these audio codecs to digital ground since we do not have separate…
Part Number: TLV320AIC24K Hi,
We are using TLV320AIC24K in our design. We are using one microphone input ADC and one DAC output in the codec.
We encountered one failure where in the microphone input ADC stopped working and there was no conversion…
Part Number: TLV320AIC24K Hi,
We are using TLV320AIC24KIPFBG4 in our design.
The datasheet does not provide VIH and VIL values for digital inputs.
Can you please let us know these values?
Regards,
Archana Rao
Part Number: TLV320AIC24K Other Parts Discussed in Thread: TLV320DAC32 Hi TI,
I need one help regarding the timing constraints given for the Serial communication of TLV320AIC24K. Here minimum time for Delay time, SCLK↑ to FS/FSD↓ is not given. Also…