Other Parts Discussed in Thread: TM4C1232D5PM I'm using a TM4C1232D5PM and a W25Q64 SPI FLASH memory.
I read blocks of 8,192 bytes from the memory. Depending on the contents of the 8K block the SPI clock will get stuck low. I have tried different SPI…
The LM3S818 is a 48 pin QFP device of the "Sandstorm" class. Here are some guidelines for migration:
www.ti.com/.../spma049a.pdf
www.ti.com/.../spma035e.pdf
From the migration guideline you will see that there is not a direct pin replacement. Take…
The Problem is because of the different clock domain of WD1 and the need to wait until data was written. This cannot accrue in WD0 but I could verify that the code works fine with WD1 on an TM4C1232D5PM.
I think there must be a way to get WD1 to work…
The Boot Configuration Register (BOOTCFG) refers to ROM Boot loader and how it starts.
I'm using a TM4C1232D5PM and on the very first power up the boot loader will execute automatically. It will also start if you erase the entire FLASH memory.
In…
Other Parts Discussed in Thread: TM4C1232D5PM , LMFLASHPROGRAMMER For others facing an issue where previously- working hardware designs now fail in the board-programming process: The updated Tiva/Stellaris DFU Windows driver supplied in the recent "XDS…
Hello Amit,
My mistake I should have explained my connection details.(Regret for not informing it in my earlier post).
According to the datasheet I desholdered the resistors R8,R10,R11,R15,R16 pins.
And I connected the X1 pins to the Target board(ie…
Other Parts Discussed in Thread: TM4C1232D5PM I am trying to communicate ti’s TM4C1232D5PM (ARM Cortex M4 based) as a master and linear’s LTC2983 as a slave by SSI protocol.
I have used SSI2 module for interfacing, port PB4,PB5,PB6,PB7 is used as CLK…
