Part Number: TMDS64GPEVM
Hello.
I want to read registers values form CPSW peripheral. For this I used command ethtool -d eth0 . This give me an output that I'm quite not understand:
root@puma:~# ethtool -d eth0 Offset Values ------ ------ 0x0000: 01 00…
Part Number: TMDS64GPEVM Hi
In our custom product based on AM6442 SoC we want to provide security level to safely store u-boot environment variables in .env file somewhere on mass storage. For now .env file is stored as plain text and this create security…
Part Number: TMDS64GPEVM Hello
I'm trying to simulate watchdog timeout to better understand how things works. I enabled watchdog driver rti_wdt and wrote some example application:
#include <stdio.h>
#include <stdlib.h>
#include <stdlib.h>
#include…
Part Number: TMDS64GPEVM
Hi,
I want to make am64xx GP-EVM(proc101c(004)) board loading Uboot through CCS.
I tried to follow the manual below.
--> https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/09_00_00_03/exports/docs/linux/Foundational_Components…
Part Number: TMDS64GPEVM Hello,
I'm using the AM64x hardware and the Ethernet-PHYs used are the DP83867 and two DP83869. I'd like to use a Linux function (or better a program) to let the PHYs blink for identification. I found out that it's possible to…
Part Number: TMDS64GPEVM Hello,
I tried the example given in the SDK for the Socket communication with CPSW LwIP.
I was wondering if I can use the CPSW with different cores at the same time? If so, how should the initialization phase change from the given…
Part Number: TMDS64GPEVM Hello,
I have a question about the DRAM initialization.
First of all: I'm trying to boot from my custom hardware, so I edited my device tree. I didn't touch the RAM settings as the same RAM as in the original hardware is used…
Hi Jakub,
Are you still having the issue?
After reviewing the pin mux it looks like your board is using IO set 2 for RGMII1. The TI EVM uses IO set 1 but that should not make a difference. I do not see an error with the pin mux.
Best Regards,
Schuyl…
Part Number: TMDS64GPEVM Hello, I'm using PCIE in the following configuration : AM64 RC (A53 Linux) <-> AM64 EP (R5 Baremetal) I want RC to access full lower 4GB of address space of EP : - Do I need to define a BAR of 4GB in EP and map it one…