Part Number: TMS320C6657
Tool/software:
This is not so much a question as it is hopefully helpfull information for anyone who might experience the same issue.
Running PDK_C665x_2_0_14 on a custom C6657 board. We had an issue when having high transmit…
Part Number: TMS320C6657 Tool/software: Hi experts,
Questions about uPP.
Q1: Is it possible to switch RX/TX using UPCTL.MODE during operation? Q2: If so, is there a recommended order for switching between RX and TX? Q3: When they actually switch UPCTL…
Part Number: TMS320C6657 Tool/software: Hello engineers from TI:
We designed a development evaluation board with a hardware architecture of DSP (C6657)+FPGA. The DSP and FPGA communicate through SRIO, but we encountered issues while testing the DSP's…
Part Number: TMS320C6657 Tool/software: Hi,
I am trying to run the TMSC6657 Core clock pins with 250 MHz. Now what exactly does the value "cpuFreqMHz" in the BOOT_PARAMS_SPI_T structure do, that is set in the boot table?
1. Is it only a reference…
Part Number: TMS320C6657 Tool/software: Hi,
We understand from past TI E2E support forums that the SPI boot operation is as follows:
After power-on, the default boot parameter table in the DSP is loaded, and some boot tables are updated to the values…
Part Number: TMS320C6657 Tool/software: Hi,
I am trying to send a MSI interrupt from the C6657 Endpoint (EP) to a remote root complex PCIe device but the MSI interrupt does not occur on the root complex side.
Here is what I did:
1. On C6657 EndPoint…
Part Number: TMS320C6657 Other Parts Discussed in Thread: LM10011 , TPSM82866A Tool/software: Hi, I am trying to use LM10011 and DC/DC to generate Smart Reflex CVDD. For DC/DC, I am thinking of selecting a power module with a built-in inductor. I am considering…
?? ? said: If DSP in srio BOOT mode , I use ccs to connect core, , the ROM boot loader work?,The emif4Cfg can init ddr?
It depends on your boot mode settings in the hardware.
If it is SRIO BOOT mode, the ROM bootloader will do some basic initialization…
tam tran said: My question is still: while 1 core access the DDR3 memory, at the same time another core has to wait for the access to DDR3, is it correct?
Yes, that is right. But that has to be maintained in your software.
SPRUGV8E (section 2.6.1) doesnot…
Dear Customer,
?? ? said: Through testing, we found that we can modify values such as DDR control register through SRIO. However, we are unable to write the values of boot cfg related registers through srio. After consulting the technical manual, we found…
