Hello,
The 1st byte is transferred without generating the TXRDY interrupt. The TX interrupt is enabled just after the data is copied to i2CDXR and moved to I2CXSR. TXRDY is generated when the transmitted data has been copied from the data transmit…
Part Number: TMS570LS1115 Team,
My customer report an issue that 570 was destroy when their product are running, they found over ten case about this issue, and send one to us to do FA, accroding to the FA report, Pin 2，3，4 and VCCIO are shorted to VSS…
Hello,
The NHET is an advanced intelligent timer. This timer is software-controlled co-processor, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. A High-End Timer Transfer Unit (HTU, acts as DMA) can…
2. Using semi-CPU mode to calculate the CRC for code in flash:
dmaEnableInterrupt(DMA_CH0, BTC); /* DMA_CH0 is highest priority */
dmaEnableInterrupt(DMA_CH1, BTC);
//using CRC semi-PCU mode
crcInit();
_enable_IRQ();
dmaEnable(); …
Hello Predeepa,
Miro and Sunil are correct. The LS11x devices do not have the ability to use the FRAY terminals as GPIOs. Sorry for the confused the message.
Part Number: TMS570LS1115 Other Parts Discussed in Thread: HALCOGEN , Is there any issues with using HalCoGen V04.06.00 for TMS570LS1115 to configure MIBSPI1 transfer groups 6 & 7 ? Have same issue on MIBSPI3.
I can successfully use transfer groups…
Hi Chuck,
Your recommended ADC register do trigger the DMA request for each group and each writes to the result memory.
But my question is not about this.
As my understanding, the whole ADC+DMA process has three phases:
ADC generate DMA request;…
