Part Number: TMUXHS4212 Hi sir,
It seems the simulation model supports only up to 0~15 GHz.
The S11 is over 0dB after 15GHz, and that is unreasonable.
However, we would like to do the simulation from 0 to 40GHz.
Is there an official model to support 0…
Part Number: TMUXHS4212 Hi~
Is the only difference between TMUXHS4212 and TMUXHS4212I the temperature range?
TMUXHS4212 :0 ~ 70C
TMUXHS4212I : -40 ~ 105C
Are the other spec like bandwidth, S-parameters the same? since there is only one datasheet for both…
Part Number: TMUXHS4212 Hi Sir,
We are using TMUXHS4212 in our HDMI 2.1 interface and as per HDMI 2.1 standard, it will work up to 12Gbps datarate.
During net length matching and max track length calculation, we required propagation delay value at 12Gbps…
Part Number: TMUXHS4212 Dear experts:
Could TMUXHS4212 switch between PCIe and 1.8V SDIO interface, and let digital signals pass it?
For M.2 WiFi modules, these two interfaces share the same pinouts. It would be convenient if TMUXHS4212 can be suitable…
Part Number: TMUXHS4212 The motherboard uses Renesas CPS-1848, and now we have to make another circuit in two on the backboard, all using Rapidio protocol, at a rate of 5Gbps. Can TMUxHS4212 be used? If not, please recommend one, thank you!
Part Number: TMUXHS4212
Now I have a signal switch design by using the TMUXHS4212, but in order to reduce the via hole, so I want to swap the signal p/n as attached file, can I swap the P/N signal on the switch? thanks!
Part Number: TMUXHS4212 Other Parts Discussed in Thread: DP83867CS I intend to use TMUXHS4212 in my design with DP83867CS (on SGMII interface) as shown in the attached diagram.Request you to confirm whether capacitive coupling is sufficient for SGMII lanes…
Part Number: TMUXHS4212 Hi,
The datasheet of TMUXHS4212 mentions 1.8V mode for Vcc on page 4, but it's not clear to us if we can supply the chip with 1.8V and use it as a USB 3.0 mux to handle connector flip in a device with a USB-C receptacle. Do we have…
Part Number: TMUXHS4212 Hi team,
Customer use TMUXHS4212 in SSD.
They wander whether the ports of A0P and A0N must correspond to PCIE's, for example, N is connected to P, P is connected to N.
If it can be done, it will be more flexible for the PCB…