Part Number: TXB0108 Tool/software: Hi,
Greetings...
We are planning to use TXB0108 in our application.
We would like to know whether the unused pins in Port A & Port B can be left open. Kindly provide your comments on the same.
Also, we would like…
Part Number: TXB0108 Other Parts Discussed in Thread: TXU0304 , SN74LXC8T245 , TXV0106 Tool/software: Hello Team,
My customer has been using two devices below and currently requires more channels.
- LSF0102DQER (I2C Only)
- TXB0108YZPR
Requirement is as…
Part Number: TXB0108 Tool/software: 1.TXB0108PWR level conversion chip, the device manual states that "external pull-up or pull-down resistors are not recommended. If it must be used, it is recommended that this value be greater than 50kΩ "(page P17…
Part Number: TXB0108 Other Parts Discussed in Thread: TXU0304 , TXU0104 , TXU0204 Hi TI team,
I have an application need converter 1.8V<->3.3V<->1.8V
In the first translator we used TXB0108.
I know that TXB0108 need high enough drive strength…
Part Number: TXB0108
Hi Team:
Please help to provide the IC power consumption.thanks.
Pc (mW)
MPN
TXB0108PWR
LSF0108PWR
SN74LV1T08DCKR
TS3A27518ETRTWRQ1
TXB0104D
TPS259814ARPWR
Part Number: TXB0108 Other Parts Discussed in Thread: TXU0304 , Hello expert,
Customer's requirement is 3.3V to 1.8V, B1 is 3.3V and A1 is 1.8V. When they are using ADS simulation, they can only choose single pin which is different from their applicaiton…
Part Number: TXB0108 Other Parts Discussed in Thread: TXV0108 , TXS0108E Hi Team, I am using TXB0108 between two cards connected in a backplane as a buffer. Below is my circuit. Both the TXBs are connected to FPGA, for card 1 it is configured as O/P, and…
Part Number: TXB0108 Other Parts Discussed in Thread: TXU0304 , TXU0104 , TXU0204 Hello expert.
I have a question for TXB0108. Please tell me.
Is it possible to use for i/f of 1.2 V and 3.3 V systems level shift in TXB0108? I am worried because VCCA min is…
Hi Parker,
Thanks for the discussion and suggestion.
I neglected to mention that DE and RE would be tied together and the FPGA would control direction of signal. The FPGA I/O is bidirectional, so the plan was to tie the R and D pins together in connecting…