Part Number: ADC12J2700 Hello,
My customer is using ADC12J2700. To confirm configuration I/O operation, they read the following register values:
Reg 0x003 (Chip type): 0x03 (expect 0x03) Reg 0x006 (Chip version): 0x03 (expect 0x13) Reg 0x00C-D …
Hi Stephen
I would compare all of the detailed signals at the FMC connector. Something must be different between the ADC EVM and your DAQ module in terms of location, signal level, etc.
I don't have that information from your board, so I don't know…
Other Parts Discussed in Thread: ADC12J2700 I have a customer who is asking the following questions:
Can you explain the difference between Table 12 and Table 13 in the data sheet? It appears that Table 13 is referring in interleaved converters? Can…
Other Parts Discussed in Thread: LMK04828 , ADC12J2700 Hi，
On the ADC side, the configurations are as follows.
I use LMK04828 provide F_DEVCLK = 1250 MHz. SYSREF=2.5/(K*F*10)=2.5/320=7.8125Mhz。
ADC12J2700 0x0021 0x00 // Initiate reset of all registers…
Other Parts Discussed in Thread: ADC12J2700 On the ADC12J2700 side, the configurations are as follows.
F_DEVCLK =1250 MHz.
Serial Interface Line Rate = 2*Fs = 2.5 Gbit/sec (per the right-most column of Table 11)
but JESD204B-Survival-Guide formula…
Other Parts Discussed in Thread: LM15851 , ADC12J1600 , ADC12J2700 , ADC12J4000 Hi,
For calculation of time from analog input to digital output, what do I have to consider besides ADC core latency?
When decimation=1, DDR1, P54=0, how long time is…
Hi Neeraj,
I appreciate your reply, but I still have more question relation between devclk and sysref.
Our clock input is being changed 270MHz to 450Mhz during one sweep time(like 10us).
It is changed continuously, not setting based.
In this case…
Other Parts Discussed in Thread: ADC12J2700
Hi,
Customer is considering FPGA with 1000 of I/0 and 24 of Serdes.
But they want to adopt several ADC12J2700 per 1 FPGA so they can use 5-lane per 1 ADC12J2700 for JESD link.
1. Can 5-lane of JESD204B…
