Hello,
I have a question and review of below block and your recommend.
Application : XG-PON and OLT Switch MUX operation.
System boards 10G-KR and connected using MUX.
Question is connection AOUT & BOUT and available A or B system recovery time…
We are bringing up boards which use 2 TI SN65LVCP114.
Issue: Packets drop and CRC errors between Line side SFP+ pairs.
Solution: Adjust VOD to 600mV and shutdown port B’s lanes (Pink Path in diagram) help reducing the issue. We still see a few…
Hello Moises-san,
I apologize for my delay. Thank you for the answers.
I believe that CS pin = Low would be only needed when the device slave address is overlapped.
Best Regards,
Kawai
Please help answer the following questions on the SN65LVCP114
1. By default on 10G SFI line, do I have to enable squelched or not? “ “FST_SW” line to high?
2. For controlling this device between using GPIO “Selx” lines or through I2C mode, which signals…
Hi,
Our customer is considering VCC(2.5V/3.3V) supplied devices for SN65LVCP114 . Are there any constraints ?
・Supply Noise, power voltage ripple
・rise time and fall time(10% to 90%)
・output current changes(A/us)
Best Regards,
Kato
When designing with the SN65LVCP114 using an older datasheet, there was no mention of needing 5k pullup/pulldown resistors on config pins, so the pins were left floating on a customer design. Now, the datasheet specifies to use them.
What will be…
Hi,
There are I2C registers which can switch the output polarity. See the registers 0x10 and 0x11 in the datasheet.
If layout is easier to swap both the SFP+ and PHY (P/N) connections as indicated there is no issue. The SN65LVCP114 does not recognize…
