Hi Eli,
How many lanes are you planning to use? This device accepts 8b/10b coding. In 10G General Purpose mode the maximum line rate in the high speed side is 9830.4Mbps @122.88/153.6MHz.
The TLK10031 is pin to pin compatible, since this device is…
Hello Takashi,
How is the MDIO pin of the FPGA configured, and does anything else share the MDIO bus? Typically MDIO is an open-drain I/O, meaning that when it is configured as an output it will either sink current to ground to pull the line low or…
Hi Elad,
This is an example script for the TLK10232EVM, basically in the GUI of this device supports Python Scripts, with the next commands the device is set in 10GBASE-KR, Link Training & Autonegotiation features disabled, adjusting some registers…
Hi Takashi,
For reference design of the TLK10232 we recommend take the TLK10232EVM as an initial guide. Please take a look into the User's guide:
Basically, this User's guide include the Schematics for the TI board (Evaluation Module), hence…
Hi ajayt,
Please take a look into the Section 10 Layout of the TLK10031 datasheet:
www.ti.com/.../tlk10031.pdf
The TLK10232EVM was designed following this guideline.
I hope this helps.
Best Regards,
Luis Omar Moran
High Speed Interface…
Hi Yuli,
TLK10232 does not have an active register to disable invalid data on XAUI output when the link is down. There are some "indirect" solutions but it means "hardware solution" (please refer to TLK10232EVM users guide to take a look in a possible…
Hi Marcel,
1. I've checked the status registers of your current configuration, basically you got decode/encode errors, loss of signal, errors in low and high speed sides.
2. Could you try changing LS_SERDES_CONTROL_2 & LS_SERDES_CONTROL_2 to adjust…
Hi Thao,
Are you trying to connect the USB dongle from the TLK10232EVM kit to your own board which includes the TLK10232 right?
As well, since the MDIO protocol requires pullup resistors, there may be a conflict of having pullup resistors on the dongle…
Hi Daniel,
Thanks for the block diagrams with various test cases. Can you confirm that the signal flow I annotated on the FPGA is correct? I have also numbed the test cases for ease of discussion.
I have a couple of questions related to your setup…
Hi Kai,
1. For reference design we suggest to take the TLL10232EVM since is the evaluation module board for TLK10xxx family, basically the TLK10031 is the single channel version of the TLK10232/034.
www.ti.com/.../TLK10232EVM
2. For application…
