DRA754: Jacinto6 registers which are persistent through warm reset PORz

Eric Best

Part Number: DRA754

Due to erratum i862, "Reset Should Use PORz", we need a workaround for warm reset on J6. The errata doc describes the workaround for detecting reset status (instead of normally using RSTSTAT) as utilizing the PMIC's registers (PMIC_BACKUP).

As an alternative, is there a register or memory within the J6 itself which will remain persistent through a PORz warm reset? That is, all rails remain within operating conditions, but PORz is logically asserted.

Please provide any thoughts to alternatives within the J6.

Thanks,

Eric

over 8 years ago

0 Mariya Petkova over 8 years ago

TI__Expert 4885 points

Hi, Eric,

I've pinged an expert to comment.

Regards,
Mariya

0 Stanislav Stilyanov over 8 years ago

TI__Mastermind 18420 points

Hi Eric,

I thought On-chip SRAM and SAR RAM should be retained during POR, however I've tested several locations in both but had no luck.

Scratchpad registers in RTC are reset to 0, so also unusable.

DSP is not clocked during POR, therefore DSP RAM is not suitable.

I cannot recall any other candidates.

Regards,

Stan

0 Piyali Goswami over 8 years ago in reply to Stanislav Stilyanov

TI__Mastermind 30245 points

Hi Stan, Eric,

There is no MMR or memory space with in the J6 device which is impervious to a PORz. During the creation of this errata, there were multiple options that were experimented with, but the PMIC Spare registers (based on the PMIC being used) was the option that was feasible in case the software is generating the warm reset/cold reset based on some decision.

TPS659039 (used with the J6 device on the TI EVM) contains BACKUP0-7 registers (8 bits each) to retain state that can be read once the J6 re-boots after the warm/cold reset converted to PORz.

Thanks and Regards,
Piyali

0 Stanislav Stilyanov over 8 years ago in reply to Piyali Goswami

TI__Mastermind 18420 points

Piyali,
Thanks for the confirmation!

regards,
Stan

0 Eric Best over 8 years ago in reply to Stanislav Stilyanov

TI__Expert 7255 points

Stan/Piyali,

Thanks for providing this info. The plan will be to use an external device such as the PMIC to set a flag as a warm reset indicator.

Regards,
Eric

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DRA754: Jacinto6 registers which are persistent through warm reset PORz