Error connecting to TDA2xx board

HI,

i am using tda2xx board ,just i have created own make file using CCS software ,but i got below error when i try debug ,please suggest me how to clear this problem

CortexA15_0: GEL Output: --->>> AM571x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> WARNING: UNKNOWN DEVICE ID (0x00000002), PLEASE UPDATE GEL FILES !!!! <<<---
CortexA15_0: GEL: Error while executing OnTargetConnect(): uninitialized GEL variable
at GEL_TextOut("\t--->>> AM571x PG%d.%d GP device <<<---\n", 0, 0, 0, 0, silicon_rev_major, silicon_rev_minor) [AM571x_startup_common.gel:106]
at AM571x_show_device_info() [AM571x_startup_common.gel:73]
at AM571x_target_connect_sequence() [AM571x_startup_common.gel:33]
at OnTargetConnect()
CortexA15_0: File Loader: Verification failed: Values at address 0x00000020 do not match Please verify target memory and memory map.
CortexA15_0: GEL: File: D:\kalai\development\GPIO_COM2\Debug\GPIO_COM2.out: a data verification error occurred, file load failed.
CortexA15_0: Unable to terminate memory download: NULL buffer pointer at 0x3aa4



thanks
kalaiventhan

HI,

thanks, i was checked another processor cortex a15 but i got same error message.please suggest how to get the output


CortexA15_0: GEL Output: --->>> TDA2xx Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> TDA2xx Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> TDA2xx PG2.0 GP device <<<---
CortexA15_0: GEL Output: --->>> The core is in non-SECURE state. <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking...
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: PER DPLL already locked, now unlocking
CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking....
CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: EVE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: EVE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output: Launch full leveling
CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output: as per HW leveling output
CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from
CortexA15_0: GEL Output: PHY_STATUSx registers
CortexA15_0: GEL Output: Launch full leveling
CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output: as per HW leveling output
CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from
CortexA15_0: GEL Output: PHY_STATUSx registers
CortexA15_0: GEL Output: One EMIF - 512MB total memory
CortexA15_0: GEL Output: Same memory mapped at 0x80000000 and 0xA0000000
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Target Connect Sequence DONE !!!!! <<<---
CortexA15_0: GEL Output: --->>> Reset occurs <<<---
CortexA15_0: GEL Output: --->>> TDA2xx PG2.0 GP device <<<---

ERROR MESSAGE

CortexA15_0: File Loader: Verification failed: Values at address 0x00000020 do not match Please verify target memory and memory map.
CortexA15_0: GEL: File: D:\kalai\development\g1\Debug__TI\g1.out: a data verification error occurred, file load failed.
CortexA15_0: Unable to terminate memory download: NULL buffer pointer at 0x3aa4

thanks
kalai