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TDA2Px M4-Cortex IPU sub-cores

Andreas Vogt57
Intellectual 730 points

Other Parts Discussed in Thread: SYSBIOS

Hi,

I have some questions about the IPU sub-cores of the M4-Cortex.

My actual setup:

•    Linux is starting the IPU1 (55020000.ipu)
•    I am not using SDK, the cores starts with an assembler start-up file
•    I am able to start code in both sub-cores IPU1_0 and IPU1_1
•    actually I am using one common stack/heap for both sub-cores.

My questions:

•    Do I need one stack/heap for each cores or can I use one common stack/heap for both sub-cores?
•    Maybe you have more information about how the context switching regarding register, stack etc. of IPU1_0 and IPU1_1 works.
•    Can you send me an example linker/startup-assembler file for the IPU?

Thanks

  • 0
    TI__Guru 55685 points
    Hi Andreas,

    You should set different stacks for both cores.
    For reference can you see <pdk>\packages\ti\csl\example\lnk_m4.cmd for linker file.
    Start up code is provided by RTS library from CGT compiler.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 730 points

    Hi Rishabh,

    in the linker file I can't find any hint that you are using separate stacks (see linker file below). Can you please send me a linker file that are using two stack sections.
    How you handle the stack pointer register in the assembler startup code, can you show me an example?


    Thanks


    -stack 0x20000 /* SOFTWARE STACK SIZE */ -> one stack
    -heap 0x20000 /* HEAP AREA SIZE */

    /* SPECIFY THE SYSTEM MEMORY MAP */

    MEMORY
    {
    IRAM_MEM: org = 0x00000000 len = 0x1000 /* RAM 0x1FBFF*/
    /*SBL will use 1 KB of space from address 0x80000000 for EVE */
    DDR3_A8: org = 0x80000400 len = (0x02000000 - 0x400) /* 32 MB */
    DDR3_DSP: org = 0x82000000 len = 0x02000000 /* 32 MB */
    DDR3_M4: org = 0x84000000 len = 0x02000000 /* 32 MB */
    DDR3_SR0: org = 0x86000000 len = 0x01000000 /* 16 MB */
    DDR3_M3VPSS: org = 0x87000000 len = 0x01000000 /* 16 MB */
    }

    /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */

    SECTIONS
    {
    .intvecs : load > IRAM_MEM
    .intc_text : load > IRAM_MEM
    .init : load > DDR3_M4

    .text : load > DDR3_M4 /* CODE */
    .data : load > DDR3_M4 /* INITIALIZED GLOBAL AND STATIC VARIABLES. */
    .bss : load > DDR3_M4 /* UNINITIALIZED OR ZERO INITIALIZED */
    /* GLOBAL & STATIC VARIABLES. */
    RUN_START(bss_start)
    RUN_END(bss_end)
    .const : load > DDR3_M4 /* GLOBAL CONSTANTS */
    .cinit : load > DDR3_M4
    .stack : load > DDR3_M4 /* SOFTWARE SYSTEM STACK */ / -> one stack
    .plt : load > DDR3_M4
    .sysmem : load > DDR3_M4
    .my_sect_ddr : load > DDR3_M4

    }

  • 0 in reply to Andreas Vogt57
    TI__Guru 55685 points

    Hi,

    This linker command file is meant for IPU1_0. You should create a separate linker command file for Core 1.
    Unfortunately I don't have an assembler example for you. You should see BIOS for that.

    Regards,
    Rishabh

  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points
    Hi,

    You can refer to BIOS ducati folder: <bios>\packages\ti\sysbios\family\arm\ducati\ for BIOS initialization code.
    In case you want to see _c_int00 routine, you can use disassembler to create one for you from existing RTS library and use it.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points
    Hi,

    I haven’t heard back from you, I’m assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out)

    Regards,
    Rishabh