RTOS/AM5746: SMP multi-core debug

Kaka

Part Number: AM5746
Other Parts Discussed in Thread: SYSBIOS, AM5749, AM5728

Tool/software: TI-RTOS

Hi TI Experts,

Please let me confirm the following question.
Now we met two issues while the SMP and multi-core debug. Would you please teach me the workaround for this?

No.1 : SMP Debug issue

Not work the Cross-Trigger in case of using the AM574x IDK. Here is the reproduced way.
1. Sync Group the Target the A15_0 and A15_1
2. Connect the target
3. Load the program for each core.
4. Run the program.
Note: When I used the AM572xIDK, it was worked well.

No.2 : Sync Group issue

When connected A15 cores with sync group, the group was forced release the sync group. And when re-select the sync group, it showed the following error in case of using AM574xIDK.
******************

CortexA15_0: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.
CortexA15_1: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.

******************

In addition to this, when connected the A15_0 core and IPU1_C0 at first and selected the sync group, it also showed the same error in case of using the AM574xIDK.
Note: When used the AM572xIDK, we did not meet this issue.

No.3 : A15 and M4 SMP debug

When tried to do the debug with SMP code for A15 and SMP code for M4 debug at the same time, it could not work.

If you have any questions, please let me know.
Best regards.
Kaka

over 6 years ago

0 Biser Gatchev-XID over 6 years ago

TI__Guru**** 393215 points

The RTOS team have been notified. They will respond here.

0 lding over 6 years ago in reply to Biser Gatchev-XID

TI__Guru* 95265 points

Kaka,

I don't know the difference between "sync group cores" and "group cores", can you try if "group cores" work for you? Also, I need to find a AM574x IDK EVM for this test (typically we used AM572x IDK EVM). The EVM differs in processor, the issue you saw is caused by CCS.

Can you clarify what CCS version you used? and what is the emulator?

Regards, Eric

0 Kaka over 6 years ago in reply to lding

Guru 24520 points

Hi Eric,

I will try it, but it will be not work the cross-triggering if used the "group cores".
I used the CCS v8.1, and emulator is on board emulator(XDS100v2).

Best regards.
Kaka

0 Kaka over 6 years ago in reply to lding

Guru 24520 points

Hi

When I used the Grope core, it showed the error as below.
***********************
[CortexA15_0] Exception occurred in ThreadType_Main.
Main handle: 0x0.
Main stack base: 0x80150c40.
Main stack size: 0x20000.
R0 = 0xe2bc3a6d R8 = 0x4037f064
R1 = 0x1ebf131d R9 = 0xffffffff
R2 = 0x6f361e05 R10 = 0x00000000
R3 = 0x4a002100 R11 = 0x80170c1c
R4 = 0x000000ca R12 = 0xf757fdc0
R5 = 0x80028908 SP(R13) = 0x80170c08
R6 = 0x00000000 LR(R14) = 0x2ff1ac2b
R7 = 0x80170c40 PC(R15) = 0x8001deb0
PSR = 0x000001df
DFSR = 0x00000a06 IFSR = 0x00000000
DFAR = 0x4a002540 IFAR = 0x00000000
ti.sysbios.family.arm.exc.Exception: line 205: E_dataAbort: pc = 0x8001deb0, lr = 0x2ff1ac2b.
xdc.runtime.Error.raise: terminating execution
***********************
Best regards.
Kaka

0 lding over 6 years ago in reply to Kaka

TI__Guru* 95265 points

Hi,

I found an AM574x IDK EVM marked with AM5749IDK REV 1.0A. I used on-board xds100v2 USB emulator, and group A15_0 and A15_1 together, when connecting, I have:

Cortex_M4_IPU1_C0: GEL Output: --->>> AM574x Cortex M4 Startup Sequence In Progress... <<<---

Cortex_M4_IPU1_C0: GEL Output: --->>> AM574x Cortex M4 Startup Sequence DONE! <<<---

Cortex_M4_IPU1_C1: GEL Output: --->>> AM574x Cortex M4 Startup Sequence In Progress... <<<---

Cortex_M4_IPU1_C1: GEL Output: --->>> AM574x Cortex M4 Startup Sequence DONE! <<<---

C66xx_DSP1: GEL Output: --->>> AM574x C66x DSP Startup Sequence In Progress... <<<---

C66xx_DSP1: GEL Output: --->>> AM574x C66x DSP Startup Sequence DONE! <<<---

C66xx_DSP2: GEL Output: --->>> AM574x C66x DSP Startup Sequence In Progress... <<<---

C66xx_DSP2: GEL Output: --->>> AM574x C66x DSP Startup Sequence DONE! <<<---

CortexA15_0: GEL Output: --->>> AM574x Cortex A15 Startup Sequence In Progress... <<<---

CortexA15_0: GEL Output: --->>> AM574x Cortex A15 Startup Sequence DONE! <<<---

CortexA15_1: GEL Output: --->>> AM574x Cortex A15 Startup Sequence In Progress... <<<---

CortexA15_1: GEL Output: --->>> AM574x Cortex A15 Startup Sequence DONE! <<<---

IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.

IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.

IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.

IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.

IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.

CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---

CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...

CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz

CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz

CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz

CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz

CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----

CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---

CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----

CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.

CortexA15_0: GEL Output: --->>> AM574x IDK EVM <<<---

CortexA15_0: GEL Output: --->>> AM574x Target Connect Sequence Begins ... <<<---

CortexA15_0: GEL Output: --->>> AM574x Begin MMC2 Pad Configuration <<<---

CortexA15_0: GEL Output: --->>> AM574x End MMC2 Pad Configuration <<<---

CortexA15_0: GEL Output: --->>> AM574x PG1.0 GP device <<<---

CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---

CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking...

CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress...

CortexA15_0: GEL Output: PER DPLL already locked, now unlocking

CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking....

CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress...

CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...

CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE!

CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---

CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---

CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---

CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress...

CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE!

CortexA15_0: GEL Output: ECC Enabled

CortexA15_0: GEL Output: Launch full leveling

CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers

CortexA15_0: GEL Output: as per HW leveling output

CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from

CortexA15_0: GEL Output: PHY_STATUSx registers

CortexA15_0: GEL Output: Launch full leveling

CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers

CortexA15_0: GEL Output: as per HW leveling output

CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from

CortexA15_0: GEL Output: PHY_STATUSx registers

CortexA15_0: GEL Output: Two EMIFs in non interleaved mode (2GB total)

CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---

CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

CortexA15_0: GEL Output: --->>> AM574x Target Connect Sequence DONE !!!!! <<<---

CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---

CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---

CortexA15_0: GEL Output: DEBUG: Clock is active ...

CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---

CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---

CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

CortexA15_1: GEL Output: --->>> AM574x IDK EVM <<<---

CortexA15_1: GEL Output: --->>> AM574x Target Connect Sequence Begins ... <<<---

CortexA15_1: GEL Output: --->>> AM574x Begin MMC2 Pad Configuration <<<---

CortexA15_1: GEL Output: --->>> AM574x End MMC2 Pad Configuration <<<---

CortexA15_1: GEL Output: --->>> AM574x PG1.0 GP device <<<---

CortexA15_1: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---

CortexA15_1: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...

CortexA15_1: GEL Output: Cortex A15 DPLL is already locked, now unlocking...

CortexA15_1: GEL Output: Cortex A15 DPLL OPP 0 is DONE!

CortexA15_1: GEL Output: IVA DPLL OPP 0 clock config is in progress...

CortexA15_1: GEL Output: IVA DPLL already locked, now unlocking...

CortexA15_1: GEL Output: IVA DPLL OPP 0 is DONE!

CortexA15_1: GEL Output: PER DPLL OPP 0 clock config in progress...

CortexA15_1: GEL Output: PER DPLL already locked, now unlocking

CortexA15_1: GEL Output: PER DPLL OPP 0 is DONE!

CortexA15_1: GEL Output: CORE DPLL OPP 0 clock config is in progress...

CortexA15_1: GEL Output: CORE DPLL OPP already locked, now unlocking....

CortexA15_1: GEL Output: CORE DPLL OPP 0 is DONE!

CortexA15_1: GEL Output: ABE DPLL OPP 0 clock config in progress...

CortexA15_1: GEL Output: ABE DPLL OPP 0 is DONE!

CortexA15_1: GEL Output: GMAC DPLL OPP 0 clock config is in progress...

CortexA15_1: GEL Output: GMAC DPLL already locked, now unlocking....

CortexA15_1: GEL Output: GMAC DPLL OPP 0 is DONE!

CortexA15_1: GEL Output: GPU DPLL OPP 0 clock config is in progress...

CortexA15_1: GEL Output: GPU DPLL already locked, now unlocking...

CortexA15_1: GEL Output: GPU DPLL OPP 0 is DONE!

CortexA15_1: GEL Output: DSP DPLL OPP 0 clock config is in progress...

CortexA15_1: GEL Output: DSP DPLL already locked, now unlocking....

CortexA15_1: GEL Output: DSP DPLL OPP 0 is DONE!

CortexA15_1: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...

CortexA15_1: GEL Output: PCIE_REF DPLL already locked, now unlocking....

CortexA15_1: GEL Output: PCIE_REF DPLL OPP 0 is DONE!

CortexA15_1: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---

CortexA15_1: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---

CortexA15_1: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---

CortexA15_1: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---

CortexA15_1: GEL Output: DDR DPLL clock config for 532MHz is in progress...

CortexA15_1: GEL Output: DDR DPLL already locked, now unlocking....

CortexA15_1: GEL Output: DDR DPLL clock config for 532MHz is in DONE!

CortexA15_1: GEL Output: ECC Enabled

CortexA15_1: GEL Output: Launch full leveling

CortexA15_1: GEL Output: Updating slave ratios in PHY_STATUSx registers

CortexA15_1: GEL Output: as per HW leveling output

CortexA15_1: GEL Output: HW leveling is now disabled. Using slave ratios from

CortexA15_1: GEL Output: PHY_STATUSx registers

CortexA15_1: GEL Output: Launch full leveling

CortexA15_1: GEL Output: Updating slave ratios in PHY_STATUSx registers

CortexA15_1: GEL Output: as per HW leveling output

CortexA15_1: GEL Output: HW leveling is now disabled. Using slave ratios from

CortexA15_1: GEL Output: PHY_STATUSx registers

CortexA15_1: GEL Output: Two EMIFs in non interleaved mode (2GB total)

CortexA15_1: GEL Output: --->>> DDR3 Initialization is DONE! <<<---

CortexA15_1: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----

CortexA15_1: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---

CortexA15_1: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---

CortexA15_1: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---

CortexA15_1: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---

CortexA15_1: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---

CortexA15_1: GEL Output: DEBUG: Clock is active ...

CortexA15_1: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_1: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_1: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---

CortexA15_1: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---

CortexA15_1: GEL Output: DEBUG: Clock is active ...

CortexA15_1: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_1: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_1: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---

CortexA15_1: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---

CortexA15_1: GEL Output: DEBUG: Clock is active ...

CortexA15_1: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---

CortexA15_1: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---

CortexA15_1: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

CortexA15_1: GEL Output: --->>> AM574x Target Connect Sequence DONE !!!!! <<<---

CortexA15_1: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----

CortexA15_1: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---

CortexA15_1: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---

CortexA15_1: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---

CortexA15_1: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---

CortexA15_1: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---

CortexA15_1: GEL Output: DEBUG: Clock is active ...

CortexA15_1: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_1: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_1: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---

CortexA15_1: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---

CortexA15_1: GEL Output: DEBUG: Clock is active ...

CortexA15_1: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...

CortexA15_1: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!

CortexA15_1: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---

CortexA15_1: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---

CortexA15_1: GEL Output: DEBUG: Clock is active ...

CortexA15_1: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---

CortexA15_1: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---

CortexA15_1: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

To test the Dhrystone:

1. Please load the C:\ti\processor_sdk_rtos_am57xx_5_00_00_15\demos\posix-smp\bin\AM572x\armv7\debug\dhry.out to A15_1 first, it will auto-run.

2. Then, load A15_0 with the same, it halt at main().

3. Run A15_0

I don't see any issue.

Regards, Eric

0 Kaka over 6 years ago in reply to lding

Guru 24520 points

Hi Eric
Which option did you select for group cores sync or only group?

0 lding over 6 years ago in reply to Kaka

TI__Guru* 95265 points

Hi,

See below screenshot, there is "Group Core(s)", this is what I used.

Regards, Eric

0 Kaka over 6 years ago in reply to lding

Guru 24520 points

Hi Eric,

Thank you for your response.
But it is different from the way described in following wiki.
processors.wiki.ti.com/.../SMP_Debug
According to this page, we need to use the "sync groups cores".

As I said, when I used the AM572x IDK with Sync Group Core, it could work well but when I used the AM574x IDK, it could not work. Would you please confirm the reason why there is a different behavior between AM574x IDK and AM572x IDK?

Also, would you please teach me the way how to debug the M4 SMP demo with following directory?
C:\ti\processor_sdk_rtos_am57xx_5_00_00_15\demos\posix-smp\bin\AM572x\m4\debug

Best regards.
Kaka

0 lding over 6 years ago in reply to Kaka

TI__Guru* 95265 points

Hi,

As you can see my update 09-21-2018 4:23 PM I tested AM5749 IDK EVM, I don't have any issue.

Regards, Eric

0 desouza over 6 years ago in reply to lding

TI__Guru**** 171044 points

Kaka,

As mentioned in the page, SMP Debug must be used only with identical cores running the exact same code. That is the reason why your scenario 3) above is not possible to be achieved with 'Sync group cores'.

I don't know if RTOS differentiates between each core when running, therefore I am unsure how 'Sync group cores' will work. Eric's attempt seems to work fine with a less involving 'Group cores', therefore I suspect there may be differences in the code.

If that does not seem to be the case, I wonder if there are any other differences between the AM572x and AM574x devices - for 'Sync group cores' work, hardware inside the device must be enabled.

Regarding the GEL files, there are minimal differences between the DDR initialization that enables ECC by default on AM574x and the configuration for interleave/non-interleave seems reversed between the two devices (apart from the change in DDR speed).

Unfortunately I do not have an AM574x board to try this out.

I will think about additional details and report back if I find anything.

Regards,
Rafael

0 Kaka over 6 years ago in reply to lding

Guru 24520 points

Hi Eric,

Could you confirm the following phenomenon?
**
1. Connect the A15_0 core
2. Connect the A15_1 core
3. Select the A15_0 and A15_1 core and set them as the sync group.n case of using AM574xIDK.
It showed as below.
******************
CortexA15_0: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.
CortexA15_1: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.
******************
**
So, I think this is problem for CCS.
Also, can you do the debug of Cross Triggering even though you choose the Group cores?

Best regards.
Kaka

0 Kaka over 6 years ago in reply to desouza

Guru 24520 points

Hi Rafael,

Thank you for your response.
As I said in other post, when select the sysn group of A15 cores, it was released the sync when it load program.
So, it seems that there is problem for CCS operation. What do you think about this?

Also, I would like to know whether customer can do the debug with both SMP program for A15 and M4 at once.
Could you please provide your comments about this?
************
No.3 : A15 and M4 SMP debug
When tried to do the debug with SMP code for A15 and SMP code for M4 debug at the same time, it could not work.
************

If you have any question, please let me know.
Best regards.
Kaka

0 lding over 6 years ago in reply to Kaka

TI__Guru* 95265 points

Kaka,

I can confirm that:
AM5749 IDK EVM + CCS 8.1 + XDS100V2 emulator, when A15_0 and A15_1 in sync group , I have below error:
CortexA15_1: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.
CortexA15_0: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.

The Dhrystone number looks right:

Starting BIOS...
Dhrystone Benchmark, Version 2.1+Thread (Language: C)
Stage 1: find good iteration count without threads
Attempting 100000 iterations
Attempting 200000 iterations
Attempting 400000 iterations
Attempting 800000 iterations
Attempting 1600000 iterations
Attempting 3200000 iterations
Attempting 6400000 iterations
Attempting 12800000 iterations
dhrystones 5763943, dmips=3103
Stage 2: find best number of threads
12800000 iterations * 1 threads
dhrystones 5656343, dmips=3045
12800000 iterations * 2 threads
dhrystones 11346384, dmips=6110
12800000 iterations * 4 threads
dhrystones 11448689, dmips=6165
dhrystone benchmark complete

Also the same setup if I use AM5728 IDK EVM, I have no such issue. The Dhrystone number looks right:
tarting BIOS...
Dhrystone Benchmark, Version 2.1+Thread (Language: C)
Stage 1: find good iteration count without threads
Attempting 100000 iterations
Attempting 200000 iterations
Attempting 400000 iterations
Attempting 800000 iterations
Attempting 1600000 iterations
Attempting 3200000 iterations
Attempting 6400000 iterations
Attempting 12800000 iterations
dhrystones 5761451, dmips=3102
Stage 2: find best number of threads
12800000 iterations * 1 threads
dhrystones 5682864, dmips=3060
12800000 iterations * 2 threads
dhrystones 11346384, dmips=6110
12800000 iterations * 4 threads
dhrystones 11451149, dmips=6166
dhrystone benchmark complete

I believe this is a CCS or CSP (chip support library) problem.

About cross triggering, the POSIX SMP example doesn't use this. I believe this is ARM core debug feature. Maybe you can open a new thread so the emulation team can look into it.

Regards, Eric

0 Kaka over 6 years ago

Guru 24520 points

Part Number: AM5746

Tool/software: Code Composer Studio

Hi TI Experts,

Please let me confirm the following issues. Would you please teach me the workaround for them?

[Issue.1]
As I reported to it on other thread, not work the Cross-Trigger in case of using the AM574x IDK.
Here is the reproduced way.
1. Sync Group the Target the A15_0 and A15_1
2. Connect the target
3. Load the program(POSIX-SMP) for each core.
4. Run the program.
Note: When I used the AM572xIDK, it was worked well.

[Issue.2]
We could not run the A15 project and M4 project at the same time.
So, would you please teach me the way to do the debug the projects for A15 and M4 with loading them at the same time?

If you have any questions, please let me know.
Best regards.
Kaka

0 lding over 6 years ago in reply to Kaka

TI__Guru* 95265 points

Kaka,

Can you explain what the issue 2 is? How do you reproduce the issue?

Regards, Eric

0 Ki over 6 years ago in reply to lding

TI__Guru**** 463941 points

lding said:
AM5749 IDK EVM + CCS 8.1 + XDS100V2 emulator, when A15_0 and A15_1 in sync group , I have below error:
CortexA15_1: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.
CortexA15_0: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.

a sync group requires a bit of HW resources. If there are not enough resources, you will get such errors when attempting to create the sync group or when trying to use global breakpoints

0 Ki over 6 years ago in reply to Kaka

TI__Guru**** 463941 points

Kaka said:
[Issue.2]
We could not run the A15 project and M4 project at the same time.
So, would you please teach me the way to do the debug the projects for A15 and M4 with loading them at the same time?

Try creating a standard (non-sync) group and then press the resume button with the top group node in context:

Thanks

0 Kaka over 6 years ago in reply to Ki

Guru 24520 points

Hi Ki,

>a sync group requires a bit of HW resources. If there are not enough resources, you will get such errors when attempting to create the sync group or when trying to use global breakpoints
I heard that the AM574x is very similar to AM572x from TI . So I would like to know the reason why AM574IDK could not support the sync group even though AM572x supported this function.

Also I could understand that if run project on each cores at the same time, we need to use the Group cores.
But if using the SMP debug for each cores (i.e. Run two SMP projects on A15 cores and M4 cores), how customer do the debug them at the same time?

Hi Eric,

Here is the way to observe this problem.
1. Connect the A15_0 core
2. Connect the A15_1 core and M4 cores.
3. Sync group(Or Group cores) the A15_0 and A15_1
4. Sync group(Or Group cores) the IPU M4 cores.
5. Load the SMP project for A15 group
6. Load the SMP project for M4 group
How should we run the those program at the same time without any errors?
When I used POSIX_SMP demo, it could not work.

Best regards.
Kaka

0 lding over 6 years ago in reply to Kaka

TI__Guru* 95265 points

Kaka,

The POSIX SMP is designed to run either on multiple A15, or C66 or M4 cores. It can't be run on multiple A15 and multiple M4 at the same time, because:
1) the code use the DDR memory, so program overlap between A15 and M4
2) the code use the same UART port for printing, conflict.

So this is not a good example to demo A15 and M4 SMP together.

Regards, Eric

0 Kaka over 6 years ago in reply to lding

Guru 24520 points

Hi Eric,

Oh, I see. Please use the following my customer example projects for M4 and A15.

0447.LC_rtos_am572x_a15.zip

7776.LC_rtos_am572x_m4.zip

I have modified the linker.cmd file including the "Debug/configPkg" folder, but I suspect that this project is also the same issue that overlap the memory space and UART port.

EXT_RAM for A15 is "0x90000000" , EXT_RAM for M4 is "0x80000000".

By the way do you have any example code which it can run on A15 and M4 cores with able to debut at the same time?

Best regards.

Kaka

0 Kaka over 6 years ago in reply to Kaka

Guru 24520 points

For Issue1, do you have any updates?
I would like to know the way to do the debug the SMP project with cross trigger.
i.e. When stop the program on Core1, the core 0 also would like to stop.

Best regards.
Kaka

0 lding over 6 years ago in reply to Kaka

TI__Guru* 95265 points

Hi,

We discussed running Dhrystone with SMP through the thread.

I am a little bit confused with the CCS projects you attached, they are template app example:
1) Template app is intended to show how to add several drivers together
2) Template app is not SMP (e.g. you CAN'T run on both A15_0 and A15_1)
3) Template app is not designed to run on different cores at the same time (e.g, you can't run on an A15 core and a M4 core)

Regarding to: By the way do you have any example code which it can run on A15 and M4 cores with able to debut at the same time?=====> We may have some IPC example, but not SMP.

What do you mean debug at the same time, if you mean something like cross-triggering. The cross-trigger only uses the same core, not between A15 and M4. If you are looking for the same example can be load into A15 and M4 at the same time, we don't have. Even you have this, I still don;t understand the term "debug at the same time".

Regards, Eric

0 lding over 6 years ago in reply to lding

TI__Guru* 95265 points

Hi Kaka,

For Issue1, do you have any updates?
I would like to know the way to do the debug the SMP project with cross trigger.
i.e. When stop the program on Core1, the core 0 also would like to stop.

Sorry I don't have any update for cross trigger. This is best to be answered by CCS team. I would suggest you open a new one for this topic. I also could transfer this thread ownership to them (then it is harder for me to track the issues follow-up).

Regards, Eric

0 Kaka over 6 years ago in reply to lding

Guru 24520 points

Hi Eric,

Thank you for your comments. And I apologize for your confusion. I had a mistake for attached file.
Here is the sample code which I have tested.
test_smp_a15.zip test_smp_M4.zip

For the meaning of "at the same time", I would like to confirm how to debug programs that A15 and M4 work in cooperation like IPC with using the CCS.

Best regards.
Kaka

0 Kaka over 6 years ago in reply to lding

Guru 24520 points

Hi Eric,

I see.

Best regards.
Kaka

0 Ki over 6 years ago in reply to Kaka

TI__Guru**** 463941 points

Eric,

Regarding:

Kaka said:
I heard that the AM574x is very similar to AM572x from TI . So I would like to know the reason why AM574IDK could not support the sync group even though AM572x supported this function.

It appears that the AM574x has a more limited number of AET resources, hence the issues experienced by Kaka regarding unable to set additional sync groups and global breakpoints (cross-triggering). Is this the case, is the AM574x more limited in this regard?

Thanks

0 lding over 6 years ago in reply to Ki

TI__Guru* 95265 points

Ki,

I looked at the AM5749 and AM5728 datasheet and technical reference manual, I didn't see any information about the AET resources. Both have: • Supports Advanced Event Triggering (AET)

Regards, Eric

0 desouza over 6 years ago in reply to lding

TI__Guru**** 171044 points

Eric, Kaka,

I can reproduce this issue exclusively on the AM574x board and in conversations here it seems the same root cause of an existing bug report DBGTRC-3912. There may be a workaround to this issue but I need to borrow the development board again to try it out.

Regards,
Rafael

0 Kaka over 6 years ago in reply to desouza

Guru 24520 points

Hi Eric, Rafael,

Thank you for your supports.
I will inform those information to our customer. Also, I am waiting for next update about workaround. In addition to this, I would like to know whether you can fix this issue by updating the software for CCS or JTAG emulation and so on.

Best regards.
Kaka

0 Kaka over 6 years ago in reply to Kaka

Guru 24520 points

Hi Eric,

Could you please provide your comments for this?
Also, regarding to your comment on previous post ("We may have some IPC example"), could you please prepare that project which it can run on CCS for A15 and M4?

Best regards.
Kaka

0 lding over 6 years ago in reply to Kaka

TI__Guru* 95265 points

Hi,

For you attached CCS projects, I think this is SMP on either A15 or M4. But you can' t run on all A15 and M4 at the same time, because you can't use the same UART port by both A15 and M4.

For IPC examples, Please refer to the “Build IPC RTOS examples” section of the IPC Quick Start Guide to build them: software-dl.ti.com/.../Foundational_Components_IPC.html

We have ex01_hello and ex11_ping examples for A15 to M4. The readme.txt file in each example’s folder contains more information about the examples, in C:\ti\ipc_3_47_02_00\examples\DRA7XX_bios_elf\ex01_hello.

To run them, they can load using CCS and then run and look at LoggerBuf in ROV.

Regards, Eric

0 Kaka over 6 years ago in reply to desouza

Guru 24520 points

Hi Eric, Rafael.

I also found similar issue on AM574DIK. When I used the "Global Breakpoint" on A15 and M4 IPC project, it showed the same error as my previous post and the program did not stop even though other core stopped.
***************
CortexA15_0: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.
***************
Please confirm it just in case.
1. Connect the A15_0
2. Connect the IPU1 cores
3. Select the A15_0 and IPU1 cores and set as grope core.
4. Load program for A15_0
5. Load program for the IPU1_C1
6. Load program for the IPU1_C0
7. Enabled the Global breakpoint all cores (A15 and IPU_C0)

-< At this time, showed the error as below.

CortexA15_0: Trouble configuring cross triggering: Error enabling this function: There is no AET resource to support this job.

8. Run the program at the same time.
9. Stop the A15_0 or IPU1_C0
-> At this time, the program did not stop at the other core.

Just in case, here is the image which I used.

6303.image.zip

Best regards.
Kaka

0 desouza over 6 years ago in reply to Kaka

TI__Guru**** 171044 points

Kaka,

Thanks to the dev team, they came up with a patch to CCS and I validated in both Windows and Linux on a DRA77xP EVM board (automotive version of the AM574x IDK).

Please unzip the attached package to the c:\ti\ccsv8 directory and let it overwrite all the files - the .zip file already contains the directory structure starting from ccs_base.

One detail, though. Make sure your AM5748IDK board has a device populated with the proper ID. To get that information do the following:

- Open a Debug session

- Right click on the Debug view and click on "Show All Cores". A new branch called 'Non debuggable devices" will be shown.

- Select the IcePick_D, right-click on it and select "Connect"

- From the Registers view, expand the branch "Core Registers" and check the IP_TAPID entry. It should show 0x0BB5002F or 0x1BB5002F.

This patch will be available in a future release of the TI Emulators component.

Hope this helps,

Rafael

dbgtrc-3912.zip

0 matusan over 6 years ago

Guru 10235 points

Part Number: AM5746

Tool/software: TI-RTOS

Hello, TI Experts,

Our customer sent us an question about AM574x Multicore behavior.

They continue to investigate SMP behavior by creating the CCS Project with TI-provided CCS patch(dbgtrc-3912.zip).

But it seems to be hang-up.

They request to investigate the attached CCS project below procedure.

- Import attached project CCS

- Connect TMDSIDK574 to PC via USB-cable.

- Click "Debug-icon"

- Open "terminal" such as tereterm

- Click "Resume-icon"

- Type "0\n" on the terminal -> Then HANG-UP! (No response from teraterm)

NG-case: hang-up!

If write "elif 1" like below in "app.c : around line 504" in the attached project & rebuild.

#elif 1

// NG

Task_setPri( (Task_Handle)gSlvTskHdl[ 0 ], TIRTOS_SUSPEND_PRI ); // test_tsk_loop_0 core0

Task_setPri( (Task_Handle)gSlvTskHdl[ 1 ], TIRTOS_SUSPEND_PRI ); // test_tsk_loop_1 core1

Task_setPri( (Task_Handle)gSlvTskHdl[ 3 ], TIRTOS_SUSPEND_PRI ); // test_tsk_sleep_3 core1

Task_setPri( (Task_Handle)gSlvTskHdl[ 2 ], TIRTOS_SUSPEND_PRI ); // test_tsk_sleep_2 core0

OK-case:

- rewrite "elif 1" like below in "app.c : around line 492" in the attached project & rebuild.

#elif 1

// no problem

Task_setPri( (Task_Handle)gSlvTskHdl[ 1 ], TIRTOS_SUSPEND_PRI ); // test_tsk_loop_1 core1

Task_setPri( (Task_Handle)gSlvTskHdl[ 0 ], TIRTOS_SUSPEND_PRI ); // test_tsk_loop_0 core0

Task_setPri( (Task_Handle)gSlvTskHdl[ 2 ], TIRTOS_SUSPEND_PRI ); // test_tsk_sleep_2 core0

Task_setPri( (Task_Handle)gSlvTskHdl[ 3 ], TIRTOS_SUSPEND_PRI ); // test_tsk_sleep_3 core1

They also found strange behavior such as "ROV:clock= too large value", after "Suspend-icon" of CCS is clicked during hung-up.

Question:

How to solve this problem?

We would appreciate if you check the attached project behavior with below their condition.

　-CCS　 Version: 8.1.0.00011 +　patch（e2e.ti.com/.../2724497

　-PDK　pdk_am57xx_1_0_11

　-SYSBIOS　bios_6_52_00_12

　-HW　AM574ｘ　IDK:　http://www.tij.co.jp/tool/jp/TMDSIDK574

　-Probe　XDS100v2 USB

Best regards,

LC_rtos_clk_not_timeout_app_am572x_a15_1024.zip

0 lding over 6 years ago in reply to matusan

TI__Guru* 95265 points

Hi,

It looks that you used AM574x A15 core for testing, the test project itself is for AM572x EVM. You don't care about GPIO, SPI. But you use the UART, are they the same instance?

Also, in the main.cfg, I saw you used:
var Board = xdc.loadPackage('ti.board');
Board.Settings.boardName = "idkAM572x";

Why don't use idkAM574x? Also, I didn't see SMP is the .cfg. I think this is just a project on A15 single core, correct, nothing to do with SMP?

This is not a TI example, but customer own code. I am not sure how much time I can spend on debug this.

Regards, Eric

0 matusan over 6 years ago in reply to lding

Guru 10235 points

Hi,

Thank you very much for your kindness.

I really appreciate your help.

We understand you found "there are something wrong in main.cfg".

Question:

Could you tell us more detail how to fix main.cfg to clarify?

We cannot find any detail official guide/documents how to write "*.cfg" to use SMP processing project.

We would appreciate if you consider to fix their "main.cfg" and check the behavior with TMDSIDK574 EVM.

Best regards,

0 lding over 6 years ago in reply to matusan

TI__Guru* 95265 points

Hi,

I thought you already knew this how to do SMP in the .cfg as you sent several programs earlier. You can also find info here: processors.wiki.ti.com/.../BIOS

We also have the POSIX SMP demo under processor_sdk_rtos_am57xx_5_01_00_11\demos\posix-smp . What I was trying to say, in your most recent attached LC_rtos_clk_not_timeout_app_am572x_a15_1024.zip, this is not a SMP project as I didn't any "BIOS.smpEnabled = true" inside the .cfg.

Regards, Eric

0 matusan over 6 years ago in reply to lding

Guru 10235 points

Hi,

Thank you very much for your kindness.

I really appreciate your help.

I checked the "main.cfg" in "LC_rtos_clk_not_timeout_app_am572x_a15_1024.zip" again

based on the below wiki which you guide.

http://processors.wiki.ti.com/index.php/SMP/BIOS

And I found SMP related statements in the "main.cfg" like below;

var BIOS = xdc.useModule('ti.sysbios.BIOS');

BIOS.smpEnabled = true;

var Core = xdc.useModule('ti.sysbios.family.arm.a15.smp.Core');

var SysStd = xdc.useModule('ti.sysbios.smp.SysStd');

var SysMin = xdc.useModule('ti.sysbios.smp.SysMin');

var LoggerBuf = xdc.useModule('ti.sysbios.smp.LoggerBuf');

Core.useSkernelCmd = false;

Core.numCores = 2;

As you mentioned, I also found inappropriate statements like below;

var socType = "am572x";

Board.Settings.boardName = "idkAM572x";

Question:

I think "main.cfg" include "SMP" statements.

So, could you consider to continue to fix their "main.cfg" and check the "NG-case: hang-up!" behavior with TMDSIDK574 EVM

including "renaming board name".

P.S. I would like to also attached "LC_rtos_clk_not_timeout_app_am572x_a15_1024.zip" again to share same undestanding with you.

Best regards,

1362.LC_rtos_clk_not_timeout_app_am572x_a15_1024.zip

0 matusan over 6 years ago in reply to matusan

Guru 10235 points

Hi,

Thank you very much for your kindness.
I really appreciate your help.

Our customer sent us the feedback from your question as below;
- Why don't use idkAM574x?

They tried to create the AM574x project from the information below E2E-thread,
because AM574x project/platform seems not to be prepared at that time.
And, they thought current recommended way is creating project from AM572x project/platform for AM574x.
e2e.ti.com/.../726266

If there are any miss-understanding or update, please tell us.

We would appreciate if you consider to continue to fix their "main.cfg" and check the "NG-case: hang-up!" behavior with TMDSIDK574 EVM.

Best regards,

0 matusan over 6 years ago in reply to matusan

Guru 10235 points

Hi,

Do you have any update about this issue？

Our customer is waiting too long.

They also checked the same issue on TMDXIDK5728.

Question:

Do you see the "NG-case: hang-up!" behavior on TMDXIDK5728?

Please check the behavior difference both "NG-case" & "OK-case" with your EVM as I explained before.

- NG-case:

　　　If write only "elif 1" like below in "app.c : around line 504" in the attached project before & rebuild.

　#elif 1 // NG

Task_setPri( (Task_Handle)gSlvTskHdl[ 0 ], TIRTOS_SUSPEND_PRI ); // test_tsk_loop_0 core0

Task_setPri( (Task_Handle)gSlvTskHdl[ 1 ], TIRTOS_SUSPEND_PRI ); // test_tsk_loop_1 core1

Task_setPri( (Task_Handle)gSlvTskHdl[ 3 ], TIRTOS_SUSPEND_PRI ); // test_tsk_sleep_3 core1

Task_setPri( (Task_Handle)gSlvTskHdl[ 2 ], TIRTOS_SUSPEND_PRI ); // test_tsk_sleep_2 core0

- OK-case:

　　　rewrite to change only "elif 1" like below in "app.c : around line 492" in the attached project before & rebuild.

　#elif 1 // no problem

Task_setPri( (Task_Handle)gSlvTskHdl[ 1 ], TIRTOS_SUSPEND_PRI ); // test_tsk_loop_1 core1

Task_setPri( (Task_Handle)gSlvTskHdl[ 0 ], TIRTOS_SUSPEND_PRI ); // test_tsk_loop_0 core0

Task_setPri( (Task_Handle)gSlvTskHdl[ 2 ], TIRTOS_SUSPEND_PRI ); // test_tsk_sleep_2 core0

Task_setPri( (Task_Handle)gSlvTskHdl[ 3 ], TIRTOS_SUSPEND_PRI ); // test_tsk_sleep_3 core1

The one of key difference seems to be on which core "Task_setPri" runs first.

We would appreciate if you tell us your current situation with this issue analysis.

Best regards,

0 matusan over 6 years ago in reply to matusan

Guru 10235 points

Hi,

Do you have any update about this issue？
Our customer is waiting too long.
I would appreciate if you tell us the current situation.

Best regards,

0 Kaka over 6 years ago in reply to lding

Guru 24520 points

Hi Eric,

Would you please support this thread?
I need to provide the answer for this question....

Best regards.
Kaka

0 Garrett Ding over 6 years ago in reply to Kaka

TI__Mastermind 43296 points

Hi Kaka,

Please refer to the update - e2e.ti.com/.../2792658 .
I am closing this thread.

Regards,
Garrett

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RTOS/AM5746: SMP multi-core debug