AM335X Versus AM37XX performance

Hi Brad,

Both processors use a Cortex-A8 with 256K L2 Cache and 64K L1 Cache.  Performance would be based on cache utilization.  Dhrystone will fit 100% into L1 cache and therefore the performance on the two parts will be identical when running the ARM at the same clock frequency.  Attached is simulation showing the Cortex-A8 MIPS for both a 16 and 32 bit DDR memory bus width.  Additionally the chart shows MIPS vs. CPU clock frequency as the clock is swept.  One chart assumes a 85% cache hit rate and another show a 45% cache hit rate.6014.A8_MIPS_vs_A8_clk_no_latency.pptx

Also there is a final chart which show how faster DDR can narrow the performance gap between 16 and 32 bit memory inferfaces.

Thanks, Jeff. That is useful. Actually the reason I posted the question was that I was seeing a large performance loss on Sitar Vs OMAP. It turned out I had one part of my code running in cacheable memory on the OMAP that was not in cacheable memory on the Sitara --- my IRQ stack. It made a large difference in performance.

Brad,

Glad you solved your issue.  You should be able to specify yourself which memorys are and are not cacheable when you set up the MMU lookup table.

Yes getting a 0% hit rate on your IRQ stack would really hurt perforamance, more so on a 16 bit memory interface.