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AM335x External Warm Reset

Daisuke Maeda
Guru 20205 points

Must the external warm reset be asserted during at least 30 cycles?

Must not the external warm reset continue being asserted until the duration defined by RSTTIME2 bit field?

Must not the external warm reset be asserted (goes low) during the duration defined by RSTTIME2 bit field?

AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. G)
http://www.ti.com/lit/ug/spruh73f/spruh73f.pdf
8.1.7.4.1 External Warm Reset
8.1.7.4.1.2 Warm Reset Sequence

Best regards,

Daisuke

 

  • 0
    Guru 20205 points

    I guess that the external warm reset is initiated by a falling edge on the nRESETIN_OUT pin.

    Does not it initiate the warm reset that the nRESETIN_OUT pin continue being asserted during the duration defined by RSTTIME2 bit field and after?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points
    Hi Daisuke,
     
    nRESETIN_OUT pin is bi-directional, open-drain. The processor detects a low level on this pin, and initiates warm reset, then the pin direction is reversed and it's the processor that keeps the pin asserted for the duration of these time intervals.
     
     
  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    I am concerned that a external warm reset causes a warm reset many times.

    TRM describes the below.

    "Caution must be used when implementing the nRESETIN_OUT as an bi-directional reset signal. Because of the short maximum time allowed using RSTTIME1, it does not supply an adequate debounce time for an external push button circuit."

    http://www.ti.com/lit/ug/spruh73g/spruh73g.pdf
    8.1.7.4.1 External Warm Reset (Page 534)

    I guess that it means that next warm reset can be caused after the duration defined by RSTTIME1 bit field.

    After the duration defined by RSTTIME1 bit field, the warm reset output is not driven by the processor and is 3-stated with weak pullup.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points
    Hi Daisuke,
     
    In the TRM paragraph you quote there is also a recommendation:
     
    "The processor could potentially start running while external components are still in reset. It is recommended that this signal be used as input only (do not connect to other devices as a reset) to implement a push button reset circuit to the AM335x, or an output only to be able to reset other devices after an AM335x reset completes."
     
    By the way, there is an updated TRM available as of yesterday.
  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    Our customer does not use an external push button circuit.

    However, the nRESETIN_OUT pin after the duration defined by RSTTIME1 bit field may be Low level because the rise time on the external reset circuit is slow.
    Does this cause the next warm reset?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points
    Hi Daisuke,
     
    I really don't understand what is the issue. I'm afraid that I can't be of much help without seeing the schematics, at least the reset circuitry.
  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    For the warm reset are two cases in the attached file available?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points
    Hi Daisuke,
     
    What are "a" and "b"? Are they external signals that the AM335X receives on the nRESETIN_OUT pin?
  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    Yes, they are.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points
    Hi Daisuke,
     
    I think that in both cases a second warm reset will be detected, because the a/b signals extend beyond the moment when the nRESETIN_OUT pin is deasserted. In my opinion the external logic that drives the a/b signals should deassert them within the 30-50 cycles time (maybe a one-shot should be used if this is not directly possible). I will ask for confirmation if this is correct, and post on this thread.
  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    I wait for the answer that you post.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points
    Hi Daisuke,
     
    I have confirmation from the design team that they are looking into your issue. They have asked for a couple of days to clarify this.
  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    Was this clarified?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points
    Hi Daisuke,
     
    No answer yet. I believe that it will be posted directly on this thread.
  • 0 in reply to Daisuke Maeda
    TI__Guru 62855 points

    The internal signal, nRESETIN_OUT, described in the Global Warm Reset section of the TRM is connected to the WARMRSTn terminal.  The warm reset sequence will begin when the WARMRSTn terminal transitions from a valid high logic level to a valid low logic level.  The AM335x will also begin driving the WARMRSTn terminal low.  The AM335x will drive a low on the WARMRSTn terminal for 30-50 cycles of the CLK_M_OSC clock plus the time defined by RSTTIME1.

    If the external warm reset source is not driving the WARMRSTn terminal when this time elapses, AM335x will stop driving the WARMRSTn terminal low and the RSTTIME2 counter will begin and the AM335x internal reset will be released after the time defined by RSTTIME2.

    If the external warm reset source is driving the WARMRSTn terminal when this time elapses, AM335x will stop driving the WARMRSTn terminal low and the RSTTIME2 counter will pause until the external source stops driving the WARMRSTn terminal low.  Once this occurs, the RSTTIME2 counter will begin and the AM335x internal reset will be released after the time defined by RSTTIME2.

    It is almost impossible to press and release a momentary push button switch connected to the WARMRSTn terminal before the RSTTIME1 and RSTTIME2 counters being clocked at 19.2, 24, 25, or 26 MHz expire.  Therefore, any switch bounce that occurs on the release may not be protected by AM335x.  For example, it may be possible for a switch bounce that occurs after AM335x stops driving the WARMRSTn terminal low to create a reset glitch that is detected by an external device when it is not detected by AM335x.  This may cause the external device to see a reset after the AM335x begins executing code or the external device may get into a bad state if the reset glitch violates the minimum reset low time.  This is the reason the TRM does not recommend using the WARMRSTn terminal as an input and output at the same time.

    Regards,
    Paul

  • 0 in reply to peaves
    Guru 20205 points

    Hi Paul and Biser,

    Thank you for your reply.

    Is any switch bounce protected for AM335x while AM335x internal reset is driven low?

    Is the rxactive field of conf_warmrstn register available for WARMRSTn?
    Is the conf_warmrstn register insensitive to warm reset?

    Best regards,

    Daisuke