NOR Boot of AM335x

Dan Donahue

Other Parts Discussed in Thread: AM3352, SYSBIOS

Greetings,

I am bringing up a proprietary board that uses the AM3352 CPU running. I have custom U-Boot and Linux BSPs based on the AM335x EVM. My board boots fine and runs the kernel fine when booting the same image from UART0, but not from NOR.

My SYSBOOT pins are mapped for the following boot order: UART0, XIP....

Using CCS (booting from NOR) I set a H/W breakpoint at 08000000 and can step through the NOR code and have verified the code is correct. It seems to taking an exception when processing the boot_params in save_boot_params, which is executed very early (lowlevel_init.S). I don't think I have a hardware issue, but rather a software one.

I have tried flashing 08000000 with both u-boot.bin and u-boot-spl.bin. Not sure if the spl one is needed based on stuff I've read on other TI forums, but tried it after the non-spl file took an exception in the same place. So it seems some basic boot parameters are not set in NOR that are when booting from UART0.

Also, I have CONFIG_ENV_IS_NOWHERE set because the ENV area of my NOR is currently blank. My goal is to write the are using 'saveenv' once I boot from NOR.

My questions:

1. Is this the right forum for this kind of sw question? If not, which one?

2. When booting for NOR is an SPL image required?

3. Is having "no environment" causing the boot_params issue?

Thanks

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi Dan,

NOR boot support is sill in the works. It's expected to be available by the end of this year. However if you search this forum, there have been people who have done it by themselves already.

0 Dan Donahue over 12 years ago in reply to Biser Gatchev-XID

Prodigy 135 points

Hi Biser,

Thank you for the response.

Yes, I am aware others on this forum have done it. I've read the threads. In those cases it appeared they were dealing with HW issues and/or using the SYSBIOS SDK, not U-Boot. I believe I am beyond any HW issues and am using U-Boot based on the AM335x EVM BSP. My question was and is pointed to anyone who has booted an AM335x out of NOR running U-Boot.

So if anyone has an AM335x booting U-Boot from NOR I'd appreciate your input.

Thanks,

Dan

0 Dan Donahue over 12 years ago in reply to Dan Donahue

Prodigy 135 points

Update: My board, whose BSP is modeled after the BeagleBone, is now booting from U-Boot from NOR. I'll give the highlights of my findings here due to the number of views and subscribers this post had and lack of answers from others.

* Programmed first sector of flash with u-boot-spl.bin

* Programmed second sector with u-boot.img (which is u-boot.bin + image header)

* Changed lowlevel_init.S to detect boot device and not process boot parameters other than device

* Added GPMC pin mux settings to enable GPMC_A1-GPMC_A10 (which translates to A17-A26)

* Enabled OE on mux chip that isolated said address lines during boot

* Modified spl code (spl.c) to handle NOR boot: read u-boot image header and copy into and jumped to DRAM

Message me if I can be of any help.

0 Jhenghyun Kim over 12 years ago in reply to Dan Donahue

Prodigy 20 points

Dear Donahue,

Thank you. Your post is very interest and it will be helpful for me.

(I am koeran, I have not good english skill)

Chould you give me your tries ?

Wait best answer.

Best Regards.

Thanks.

0 Chandrashekhar V1 over 11 years ago in reply to Biser Gatchev-XID

Intellectual 640 points

Hi Biser,

I too have similer issue with the nor flash booting.

Now am trying to boot from UART and flash the NOR flash. Kindly update me with boot arguments and steps to flash NOR flash using UART.

Here below are the prints from my board,

*******************************************************************************************

U-Boot 2013.10-00190-g7ea7cb2-dirty (Jun 11 2014 - 21:24:44)

I2C:   ready
DRAM: 256 MiB
board_init.
Flash: 32 MiB
NAND: nand: error: Unable to find NAND settings in GPMC Configuration - quitting
0 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Error - No Valid Environment Area found
*** Warning - bad CRC, using default environment

Net:   usb_ether
Hit any key to stop autoboot: 0
U-Boot#
U-Boot# print
arch=arm
baudrate=115200
board=am335x
board_name=am335x
boot_fdt=try
boot_targets= mmc0 nand
bootcmd=for target in ${boot_targets}; do run bootcmd_${target}; done
bootcmd_mmc0=setenv devnum 0; setenv rootpart 2; run mmc_boot;
bootcmd_nand=run nandboot;
bootcmd_usb=setenv devnum 0; run usb_boot;
bootdelay=3
bootdir=/boot
bootenv=uEnv.txt
bootfile=zImage
bootpart=0:2
console=ttyO0,115200n8
cpu=armv7
dfu_alt_info_emmc=rawemmc mmc 0 3751936
dfu_alt_info_mmc=boot part 0 1;rootfs part 0 2;MLO fat 0 1;MLO.raw mmc 100 100;u-boot.img.raw mmc 300 400;spl-os-args.raw mmc 80 80;1
dfu_alt_info_nand=NAND.SPL part 0 1;NAND.SPL.backup1 part 0 2;NAND.SPL.backup2 part 0 3;NAND.SPL.backup3 part 0 4;NAND.u-boot-spl-os0
dfu_alt_info_ram=kernel ram 0x80200000 0xD80000;fdt ram 0x80F80000 0x80000;ramdisk ram 0x81000000 0x4000000
ethact=usb_ether
fdt_high=0xa0000000
fdtaddr=0x80F80000
fdtfile=undefined
findfdt=if test $board_name = A335BONE; then setenv fdtfile am335x-bone.dtb; fi; if test $board_name = A335BNLT; then setenv fdtfile
importbootenv=echo Importing environment from mmc ...; env import -t $loadaddr $filesize
loadaddr=0x80200000
loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}
loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}
loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz
mmc_boot=setenv devtype mmc; if mmc dev ${devnum}; then run mmcargs;run scan_boot; run mmcboot;setenv mmcdev 1; setenv bootpart 1:2;i
mmcargs=setenv bootargs console=${console} ${optargs} root=${mmcroot} rootfstype=${mmcrootfstype}
mmcboot=mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environmen;
mmcdev=0
mmcloados=run mmcargs; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then bootz ${loadaddr} - ${fdtaddr};
mmcroot=/dev/mmcblk0p2 ro
mmcrootfstype=ext4 rootwait
mtdids=nand0=nand.0
mtdparts=mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os)
nandargs=setenv bootargs console=${console} ${optargs} root=${nandroot} rootfstype=${nandrootfstype}
nandboot=echo Booting from nand ...; run nandargs; nand read ${fdtaddr} NAND.u-boot-spl-os; nand read ${loadaddr} NAND.kernel; bootz}
nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048
nandrootfstype=ubifs rootwait=1
netargs=setenv bootargs console=${console} ${optargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp
netboot=echo Booting from network ...; setenv autoload no; dhcp; tftp ${loadaddr} ${bootfile}; tftp ${fdtaddr} ${fdtfile}; run netar}
nfsopts=nolock
partitions=uuid_disk=${uuid_gpt_disk};name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}
ramargs=setenv bootargs console=${console} ${optargs} root=${ramroot} rootfstype=${ramrootfstype}
ramboot=echo Booting from ramdisk ...; run ramargs; bootz ${loadaddr} ${rdaddr} ${fdtaddr}
ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M
ramrootfstype=ext2
rdaddr=0x81000000
rootpart=2
rootpath=/export/rootfs
scan_boot=echo Scanning ${devtype} ${devnum}...; for prefix in ${bootdir}; do for script in ${bootfile}; do run script_boot; done; d;
script_boot=if load ${devtype} ${devnum}:${rootpart} ${loadaddr} ${bootdir}/${bootfile}; then run findfdt; load ${devtype} ${devnum};
soc=am33xx
spiargs=setenv bootargs console=${console} ${optargs} root=${spiroot} rootfstype=${spirootfstype}
spiboot=echo Booting from spi ...; run spiargs; sf probe ${spibusno}:0; sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; bootz ${loa}
spibusno=0
spiimgsize=0x362000
spiroot=/dev/mtdblock4 rw
spirootfstype=jffs2
spisrcaddr=0xe0000
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
stderr=serial
stdin=serial
stdout=serial
usb_boot=setenv devtype usb; run usb_init; if usb dev 0; then run usbargs;run scan_boot; bootz ${loadaddr} - ${fdtaddr}; fi
usb_init=usb start 0;
usbargs=setenv bootargs console=${console} ${optargs} root=${usbroot} rootfstype=${usbrootfstype}
usbnet_devaddr=d0:39:72:0f:c7:4c
usbroot=/dev/sda2 rw
usbrootfstype=ext4 rootwait
vendor=ti
ver=U-Boot 2013.10-00190-g7ea7cb2-dirty (Jun 11 2014 - 21:24:44)
*******************************************************************************************************

Rgds,

chandra

0 Steve Kipisz over 11 years ago in reply to Chandrashekhar V1

TI__Genius 15510 points

Chandra,

This assumes u-boot from SDK 7.0, the steps I've used in the past:

Use UART0 to download spl/u-boot that see the NOR. Then the commands from a u-boot prompt to flash the board:

protect off all

erase all

loady

use your terminal program to download u-boot.bin that was built to boot from NOR

use ymodem

cp.b 0x80200000 0x08000000 <size in hex>

use your termianl program to download zImage

use ymodem

cp.b 0x80200000 0x080c0000 <size in hex>

use your terminal program to download jffs2 file system

use ymodem

cp.b 0x80200000 0x084c0000 <size in hex>

protect on all

Then reboot the board.

Steve K.

0 Chandrashekhar V1 over 11 years ago in reply to Steve Kipisz

Intellectual 640 points

Hi Steve,

Even I was also trying for the same.

I repeated the steps you given above and all steps are executed successfully but after the reboot board(changed boot config to 01100) is not able to boot from NOR flash. I tried flashing only u-boot.bin.

here below are boot messages,

_____________________________________________________________________________

____________________________________________________________________________

Rgds,

chandra

0 Chandrashekhar V1 over 11 years ago in reply to Chandrashekhar V1

Intellectual 640 points

Hi Steve,

Today I probed the data lines and address lines. looks like processor is trying to read from NOR.

Is there any thing else I can try to boot from NOR flash.

Steps followed by me as any issue?

Thanks & Rgds,

chandra

0 Chandrashekhar V1 over 11 years ago in reply to Chandrashekhar V1

Intellectual 640 points

Hi Steve,

Here below is my NOR configuration, Attached the NOR(S29GL256S90DHI02 )datasheet

    #undef CONFIG_SYS_NO_FLASH
   #define CONFIG_CMD_FLASH
   #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
   #define CONFIG_SYS_FLASH_PROTECTION
   #define CONFIG_SYS_FLASH_CFI
   #define CONFIG_FLASH_CFI_DRIVER
   #define CONFIG_FLASH_CFI_MTD
   #define CONFIG_SYS_MAX_FLASH_SECT   256
   #define CONFIG_SYS_MAX_FLASH_BANKS   1
   #define CONFIG_SYS_FLASH_BASE       (0x08000000)
   #define CONFIG_SYS_FLASH_CFI_WIDTH   FLASH_CFI_16BIT
   #define CONFIG_SYS_MONITOR_BASE       CONFIG_SYS_FLASH_BASE
   #ifdef CONFIG_NOR_BOOT
   #define CONFIG_ENV_IS_IN_FLASH
   #define CONFIG_ENV_SECT_SIZE       (128 << 10)   /* 128 KiB */
   #define CONFIG_ENV_OFFSET       (512 << 10)   /* 512 KiB */
   #define CONFIG_ENV_OFFSET_REDUND   (768 << 10)   /* 768 KiB */
   #ifdef MTDIDS_DEFAULT
   #undef MTDIDS_DEFAULT
   #endif
   #define MTDIDS_DEFAULT           "nor0=physmap-flash.0"

   #ifdef MTDPARTS_DEFAULT
   #undef MTDPARTS_DEFAULT
   #endif
   #define MTDPARTS_DEFAULT       "mtdparts=physmap-flash.0:" \
                       "512k(u-boot)," \
                       "128k(u-boot-env1)," \
                       "128k(u-boot-env2)," \
                       "4m(kernel),-(rootfs)"
   #endif

rgds,

chandra

S29GL256S90DHI02.pdf

0 Chandrashekhar V1 over 11 years ago in reply to Chandrashekhar V1

Intellectual 640 points

Hi Steve,

There is a assembly code written in MUX.c file for NOR pinmux. Is this code still valid for our flash memory which we are using on board.

enable_norboot_pin_mux function is called by s_init which is in ./arch/arm/cpu/armv7/am33xx/board.c

#if defined(CONFIG_NOR_BOOT)
void enable_norboot_pin_mux(void)
{
   /*
   * The ROM will only have set up sufficient pinmux to allow for the
   * first 4KiB NOR to be read, we must finish doing what we know of
   * the NOR mux in this space in order to continue. We do this in
   * assembly to avoid having to play linker games to ensure that all
   * functions and data sections are in this special area.
   */
   asm("stmfd      sp!, {r2 - r4}");
   asm("movw       r4, #0x8A4");
   asm("movw       r3, #0x44E1");
   asm("orr        r4, r4, r3, lsl #16");
   asm("mov        r2, #9");
   asm("mov        r3, #8");
   asm("gpmc_mux: str     r2, [r4], #4");
   asm("subs       r3, r3, #1");
   asm("bne        gpmc_mux");
   asm("ldmfd      sp!, {r2 - r4}");
}
#endif

Here below are my pin muxes in U-boot code. Which has little different than Beagle bone nor cape.

    {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */
   {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A1 */
   {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A2 */
   {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A3 */
   {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A4 */
   {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A5 */
   {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A6 */
   {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A7 */
   {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A8 */
   {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A9 */
   {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE},       /* NOR_A10 */
   {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
   {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A12 */
   {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A13 */
   {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A14 */
   {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A15 */
   {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A16 */
   {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A17 */
   {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A18 */
   {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A19 */
   {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD0 */
   {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD1 */
   {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD2 */
   {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD3 */
   {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD4 */
   {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD5 */
   {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD6 */
   {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD7 */
   {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD8 */
   {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD9 */
   {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD10 */
   {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD11 */
   {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD12 */
   {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD13 */
   {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD14 */
   {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD15 */

   {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE},   /* NOR_CE */
//   {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
   {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
//   {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
   {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)},    /* NOR_WEN */
   {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
   {-1},

rgds,

chandra

0 Steve Kipisz over 11 years ago in reply to Chandrashekhar V1

TI__Genius 15510 points

I have to spend a little bit more time looking at your pin-muxing. When you change mux.c you also need to change the assembly code in board.c. Maybe this could be commented better in the code. For XIP boot, the boot ROM only pin-muxs A0-A11 for non-multiplex NOR or AD0-AD15 for multiplex NOR. So for the case of non-multiplex NOR, the rest of the pin-mux must be done within the first 4k of address space. For multiplex NOR, the rest of pin-mux must be done within the first 64k of address space. So the assembly code in board.c will pin-mux within the first 4k of address space so it should work for both. BUT...the code assumes a multiplex NOR that is used for Beaglebone NOR module. If you have a non-multiplex NOR, you have to change the assembly code to pin-mux for non-multiplex NOR.

Steve K.

0 Chandrashekhar V1 over 11 years ago in reply to Steve Kipisz

Intellectual 640 points

Thanks Steve,

Do you have assembly code for non-multiplesed NOR? If your provide this assembly code then it will help and move faster in our design.

I am debugging from JTAG it looks like code is able to execute from NOR flash but stuck in the memory address 0x08000224.

Also did the single step in Disassembly, here below are the results,(Attached the image)

It loops in the PC address 0x08000220,0x08000224 and jumps to 0x08000010 and comes back to 0x08000220

rgds,

chandra

0 Mark Utter over 11 years ago in reply to Chandrashekhar V1

TI__Expert 7155 points

Chandra,

The below needs to be done by the assembly code to configure the upper address balls for MUX_MODE2 NOR flash boot.

Configure ZCZ Ball Mode# Pad Control Reg Adress Offset

LCD_DATA8->GPMC_A12 U1 1 0x8C0

LCD_DATA9->GPMC_A13 U2 1 0x8C4

LCD_DATA10->GPMC_A14 U3 1 0x8C8

LCD_DATA11->GPMC_A15 U4 1 0x8CC

LCD_DATA12->GPMC_A16 V2 1 0x8D0

LCD_DATA13->GPMC_A17 V3 1 0x8D4

LCD_DATA14->GPMC_A18 V4 1 0x8D8

LCD_DATA15->GPMC_A19 T5 1 0x8DC

MMC0_DAT3->GPMC_A20 F17 1 0x8F0

MMC0_DAT2->GPMC_A21 F18 1 0x8F4

MMC0_DAT1->GPMC_A22 G15 1 0x8F8

MMC0_DAT0->GPMC_A23 G16 1 0x8FC

MMC0_CLK->GPMC_A24 G17 1 0x900

Here's the corresponding assembly code to configure balls:

asm("stmfd sp!, {r2 - r4}"); // save register context

// Configure GPMC[A19:12] balls
asm("movw r4, #0x8C0"); // pad config registers begin @ address 0x44e108c0
asm("movw r3, #0x44E1");
asm("orr r4, r4, r3, lsl #16");
asm("mov r2, #9"); // set 8 balls to mode 1 with pull disabled
asm("mov r3, #8");
asm("gpmc_mux: str r2, [r4], #4");
asm("subs r3, r3, #1");
asm("bne gpmc_mux");

// Configure GPMC[A24:20] balls

asm("movw r4, #0x8F0"); // pad config registers begin @ address 0x44e108f0
asm("movw r3, #0x44E1");
asm("orr r4, r4, r3, lsl #16");
asm("mov r2, #9"); // set 5 balls to mode 1 with pull disabled
asm("mov r3, #5");

asm("gpmc_mux1: str r2, [r4], #4");
asm("subs r3, r3, #1");
asm("bne gpmc_mux1");

asm("ldmfd sp!, {r2 - r4}"); // restore register context

Please review & try it out.

Regards,

Mark

0 Chandrashekhar V1 over 11 years ago in reply to Mark Utter

Intellectual 640 points

Hi Mark,

Today I tried these changes but no luck. Still I am not able to boot from NOR flash.

I hope you are aware of NOR address bus A0 is connected to Am335x address bus A1. May be becuase of 16bit access. But it is different in beagle cape.

Rgds,

Chandra

0 Chandrashekhar V1 over 11 years ago in reply to Chandrashekhar V1

Intellectual 640 points

Sorry,

My mistake NOR booting is working but taking a few second delay to boot may be because I have boot configs set for 01100b(USB0,NAND,XIP,NANDI2C).

Thanks for everyone's support I really appreciated.

Rgds,

chandra

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NOR Boot of AM335x