NAND read time Problem

Keldy,

Its possible to speed the NAND read performance by optimizing the driver. You can read the 15MB data in almost less than 2 seconds after optimizations

Hi,

can you give me more hints and direction that where i should start from in order to optimize my nand drive?

Thanks and Regards

Keldy

Keldy,

You've to optimize mainly the read_buf() function to achieve faster throughput. I'm not sure about your code, but I have seen code where it implements nand_wait() using ndelay() by just polling. This is really un-optimized and you should be using the wait pin from the NAND. But these two steps will give a good improvement. Plus if you enable instruction cache, then it will also help. 

Hi Thomas

could you please tell me why we may not enable D-Cache?

in starterware example when I enable D-Cache, the code does not work properly.

thanks,

Amin

Amin,

If you enable D-cache just like that, what will happen is that, even all the memory mapped I/O registers will cached, which will result in your drivers not working as expected. So inorder to enable d-cache properly, you've to enable MMU and then define a static page table which will define the memory regions to be cached. Then caching will be performed only for cacheable regions defined in the page table.

   Thomas

You are right, but I did what you said. In my code I defined a memory region for NAND (GPMC map) as below snippet code:

    REGION regionNAND= {
                           MMU_PGTYPE_SECTION, 0x10000000, 512,  //0x10000000  is address of NAND memory map
                           MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_NON_CACHEABLE, MMU_NON_CACHEABLE),
                           MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
                           (unsigned int*)pageTable
                          };

    MMUInit((unsigned int*)pageTable);

    /* Map the defined regions */
    MMUMemRegionMap(&regionDdr);  // based om starterware example
    MMUMemRegionMap(&regionOcmc); // based om starterware example
    MMUMemRegionMap(&regionDev); // based om starterware example
    MMUMemRegionMap(&regionNAND); //added line by me

    /* Now Safe to enable MMU */
    MMUEnable((unsigned int*)pageTable);

As you see I used "MMU_NON_CACHEABLE" for memory type, however my code does not work. Just when I don't enable D-cache, everything is OK.

What is wrong in my code?

Thanks

Amin

Amin,

I'm not sure about Staterware's implementation. Need to see the code more closely to understand whats going wrong. But why are you attempting this? Is it just for NAND throughput improvement? If so, what is the NAND through put that you are targeting? 

Hi Thomas

NAND FLASH is just one part of my system and I need the processor(AM3352) execute instructions as fast as possible for other parts. So enabling cache for data and instruction will help this process, am I right?

However I use NAND with part numberMT29F2G08 which read a page(2048 byte) typically in 25 us.

Thanks,

Amin

Amin,

If you are caching the buffer that you are using for writing to NAND, then after the buffer is filled it has to be flushed to memory if you are using DMA. So it will be always better to use uncached buffers for NAND read/writes. 

What is the  throughput that you are getting now?

Hi Thomas,

Thanks for your reply.  I do not know how define uncached buffer.

Currently The measured throughput of read operation  is about 200 KByte/s. Nand   FLASH Datasheet expresses it has to be 80 MByte/s.(each 2048 byte page in 25us).

Thanks,

Amin

Amin,

200KB/sec is too slow. You can easily achieve 10-15MB/sec. I don't think you need to enable data cache to achieve this. You have to optimize the NAND driver to achieve this.

Hi Thomas,

I use am335x, and the nand xfer_type default config is  NAND_OMAP_PREFETCH_POLLED as below.

enum nand_io {

NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
NAND_OMAP_POLLED, /* polled mode, without prefetch */
NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
};

If I config the xfer_type to NAND_OMAP_PREFETCH_DMA mode, the kernel msg will show as below.

[ 0.869659] omap_set_dma_dest_burst_mode: un-supported SDMA wrapper
[ 0.876220] omap_set_dma_src_burst_mode: un-supported SDMA wrapper

Trace the kernel code seems am335x doesn't support  "omap_set_dma_dest_burst_mode" and DMA mode.

That will get bad performance than am3517.

Do you know why am335x doesn't support DMA mode or I mistake something?

Thanks.

Thomas,

I expected the nandlib in starterware is optimized.! However, what do you recommend me? DMA mode or CPU mode for data transferring?

Can I find s suitable driver in somewhere?

Thanks

Amin

Amin,

You can try both DMA or CPU mode. CPU mode will be simpler. I'm not sure about optimized NAND driver availability.

Dear Thomas,

Am335x Linux driver seems no support DMA mode for NAND flash.
Do you know there is any patch for DMA mode?

Thanks.

Ted,

I am not sure about AM335x Linux DMA mode. I'm not sure about the availability of the patch. But instead you can start without DMA and optimize the current poll based code  to get a better throughput.

Dear Renjith,

Thanks your reply.

Yes, I am trying to optimize the nand flash throughput. But until now only get extra 10% performance on am335x chip.
Am335x 's nand flash controller is definitely different with  am3517.

Ted,

If you can send one of your hardware, we can optimize the drivers throughput for you. 

Dear Renjith,

Thanks much.

How much throughput do you expect?

The below is copy from wiki . (http://processors.wiki.ti.com/index.php/AM335x-PSP_04.06.00.08_Features_and_Performance_Guide)

Performance Benchmarks

Please refer MTD Test Setup before proceeding.

Ted,

8-10MB/sec with little effort and close to 15MB/sec if more effort is put.

hi, 

    we also faced this problem, nand read 5M file cost 7 seconds in uboot, we've changed nand_wait() function, but it seems not increased,

    Does it have any patch? or how to increase nand read speed in uboot?

    We are using u-boot-2012.10-psp05.06.00.00

Have a look at this thread.

http://e2e.ti.com/support/arm/sitara_arm/f/791/p/273108/983585.aspx#983585