Confusion about I/O direction of SPI pins

Hi Felix,

Which processor pins are you using to mux the SPI1 signals?

Please check if these pins are muxed correctly from user space:

1. Mount the debugfs: mount -t debugfs none /sys/kernel/debug/
2. Check the current pinmux configurations for your pins:
cat /sys/kernel/debug/omap_mux/<pin_name>

This should give you information about the current mux configuration for the pin.

Best regards,
Miroslav

Hello Miroslav,

Thanks for this tip. When I enter 'cat /sys/kernel/debug/omap_mux/mcasp0_fsx' I get the following:

name: mcasp0_fsx.spi1_d0 (0x44e10994/0x994 = 0x0003), b NA, t NA
mode: OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT
signals: mcasp0_fsx | NA | NA | spi1_d0 | mmc1_sdcd | NA | NA | gpio3_15

Doesn't this look fine? According to this I would expect SPI1 data to be output on SPI1_D0.

regards Felix

Hello Biser,

I don't understand this. What do you mean by 'have you set your pins to SPI mode'? CS and CLK are working as expected.

regards, Felix

When I enter 'cat /sys/kernel/debug/omap_mux/mcasp0_aclkx' I get this:

name: mcasp0_aclkx.spi1_sclk (0x44e10990/0x990 = 0x0023), b NA, t NA
mode: OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLDOWN
signals: mcasp0_aclkx | NA | NA | spi1_sclk | mmc0_sdcd | NA | NA | gpio3_14

Looks fine to me. Just to make sure I explained correctly: the SOC is running as SPI master and do not see anything happen on pin SPI1_D0 which is supposed to output the serial data. CS and CLK are working.

For testing purposes I have configured SPI1_D0 to be be GPIO3_15. Setting it to output mode I can see on the oscilloscope that it toggles when I write 0/1 to it. At least I am sure now that the pin is working, i.e. it must be a wrong configuration in software.

Looking at the 'board-am225xevm.c" file I can find for example the following pin configuration for SPI0:

static struct pinmux_config spi0_pin_mux[] = {
    {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
                            | AM33XX_INPUT_EN},
    {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
                            | AM33XX_INPUT_EN},
    {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
                            | AM33XX_INPUT_EN},
    {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
                            | AM33XX_INPUT_EN},
    {NULL, 0},

But how is this supposed to work? Who or what configures D0 or D1 to be MOSI (the output)?

regards Felix

Hello Biser,

I knew that but did somehow not fully realize. The TRM (version h) at 24.4.1.18 states that after reset DP0 is 0 and DPE1 is 1. My conclusion was that SPIDAT[0] gets selected as transmission line. So far this is correct, but in file 'spi-omap2-mcspi.c' theses settings get modified in function 'omap2_mcspi_setup_transfer':

    l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
    l |= OMAP2_MCSPI_CHCONF_DPE0;

This was exactly my problem as this code 'reverts' the default settings of DPE0/1. After the following modification to the code my LC display finally accepts configuration commands from the SOC:

    l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE0);
    l |= OMAP2_MCSPI_CHCONF_DPE1;

Thank you very much for pushing me into the right direction, Felix

Just some additional information for those struggling with SPI data pin direction:

Meanwhile I'm on kernel 4.5 using device tree. There is no more need to modify any code, just add the ti,pindir-d0-out-d1-in property to the corresponding SPI device. The property is described in the binding documentation found at ./Documentation/devicetree/bindings/spi/omap-spi.txt.

My DTS file therefore contains the following code:

&spi1 {
    pinctrl-names = "default";
    pinctrl-0 = <&spi1_pins>;
    ti,pindir-d0-out-d1-in;
    status = "okay";

    cfaf240320a032t {
        compatible = "crystalfontz,cfaf240320a032t";
        reg = <0>;
        spi-max-frequency = <1000000>;
        // SPI mode 3
        spi-cpol;
        spi-cpha;
        status = "okay";
    };
};

Et voilà, it works! Hope this might help somebody, Felix