AM3517 Byte Enable Outputs

When accessing a asynchronous memory device using the GPMC interface (asynchronous, 8 or 16 bit, multiplexed mode), we never see the nBE0 or nBE1 pins transition from high to low during the read/write bus cycle.  The nBE0 and nBE1 pins are both eternally set at a logic zero. I checked the PINMUX register configuration and confirmed both nBE0 and nBE1 pins are set up as outputs, internal pull-ups enabled and active, and the pin mux is set to b000 for operational mode 0.  We are not experiencing any issues with our GPMC accesses, but we expected to see the nBE0 and nBE1 pins default to a logic high and drive to logic low during valid GPMC accesses. Could TI confirm if the behavior we are observing of the nBE0 and nBE1 signals is correct, or do we have a configuration issue??