• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 555 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CM_PER_EMIF_FW_CLKCTRL register

Paul Withers
Prodigy 30 points

Other Parts Discussed in Thread: AM3352

In the starterware package header files there is a register named CM_PER_EMIF_FW_CLKCTRL at offset 0xd0 - this is not in the AM3352 TRM (rev J).  What is it and do I actually need to initialize it?

Thanks,

Paul Withers

  • 0
    TI__Guru**** 393215 points
    Hi Paul,
     
    This link http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips describes all the registers that need to be configured for the DDR EMIF to function properly. Registers not mentioned should be left in their default state.
     
    For Starterware questions there is a dedicated forum: http://e2e.ti.com/support/embedded/starterware/default.aspx.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 30 points

    Just FYI - the wiki link does not list the PRCM and CM registers to enable the EMIF module clocks and the link from that page to the recommended initialization procedure is broken.  References to this mysterious register are not only in the starterware package - but are elsewhere in TI supplied firmware which has EMIF module clock initialization.

    I shall assume that the various TI firmware packages are wrong and that the TRM is correct as I have successfully initialized the EMIF for DDR2 without initializing this undocumented register.

    My concern is because I am seeing less performance than I expected so I am thinking that I have mis-configured it somehow.  The fastest time I have been able to achieve between consecutive random single word read and writes, but in the same bank, is around 30 to 50 DDR clocks (at 200MHz DDR2) and so far everything seems to be configured correctly, but this seems to be at least 2:1 slower than one would expect. I am running some test code from the internal SRAM and with ICache enabled (but Dcache and MMU disabled) to perform this test.

    Thanks

  • 0 in reply to Paul Withers
    Prodigy 90 points

    Search for the string with name  CM_PER_EMIF_FW_CLKCTRL will the give you the register, else it was mentioned in section 8.1.12.1.38

    Thanks