AM3517-05 LAN 50M reference clock problem(LAN8700 or LAN8720)

Hi Peter,

The AM35X RMII 50MHz clock is not generated from the processor, it comes from the PHY. TI does not manufacture the PHY's you have listed, so perhaps you should direct this question to the manufacturer of those parts.

As a suggestion, in reference designs there is a serial resistor on this clock line. Do you have one on your board?

Hello Gatchev-XID,

         Thanks for your reply.

          Yes,you are right.The AM35X RMII 50MHz clock is not generated from the processor, But the AM35X Ethernet like only support RMII interface, so what even you choose any Ethernet chips that the AM35X RMII 50MHz must need by AM35X processor. and we have found the LAN8700(taken by oscillation.) and LAN8720(taken by 25MHZ  crystal) are recommanded by TI reference design and those two chips have the same problems on the developer board(LOGIC and MISTRAL) by your recommanded.

        Our LAN designs are the same as reference designs, so i think  the other customer will have the same problems like us, so  we need guys help and share some experiences.

        Thanks again.

        Best Regards!

        Peter Liu

- Add a XTAL oscillator with 50MHz to your board. Use a shielded one. (You have already done that?)

- On the output of the oscillator (3.3V), use a ferrite bead.

- Feed the clock input of the PHY and the CPU with the signal from the ferrite bead.

- Tune the inductance of the ferrite bead so that the resonance with the wire capacitance of the clock line is above 50 MHz (maybe ca. 70 MHz).

- With your oscilloscope, you will see a 5V 'sine' wave at the clock line. You MUST use a low-capacitance active probe for your scope.

- As a start point, try a ferrite bead like Tayo Yuden BK1005HM241 or Wuerth 742843122.

That's it. The 5V sine wave will be clipped at the clock inputs of the PHY and the CPU, and will give a good clock source. The harmonic noise will be minimised due to the LC filter.

If you use the ICPLUS IP101A PHY, which has an own pin for 50 MHz clock out, you do not need an extra XTAL oscillator, only a XTAL.

You might also do a redesign of your PCB and route the clock line on an inner layer, guarded with GND lines left/right.

regards

Wolfgang

Hello Wolfgang,

         Thanks for your suggestions.

        we reply your sugestions as belows:

- Add a XTAL oscillator with 50MHz to your board. Use a shielded one. (You have already done that?)

      [A] We used shielding can, the existing PCB layout can’t suppress the harmonic noise completely

- On the output of the oscillator (3.3V), use a ferrite bead.

[A] Done

- Feed the clock input of the PHY and the CPU with the signal from the ferrite bead.

[A] Done

- Tune the inductance of the ferrite bead so that the resonance with the wire capacitance of the clock line is above 50 MHz (maybe ca. 70 MHz).

[A] The best way to suppress the noise source. Shift the resonance frequency will affect other band sensitivity.

- With your oscilloscope, you will see a 5V 'sine' wave at the clock line. You MUST use a low-capacitance active probe for your scope.

[A] Thanks.

- As a start point, try a ferrite bead like Tayo Yuden BK1005HM241 or Wuerth 742843122.

[A] We use Murata SMD ferrite bead.

That's it. The 5V sine wave will be clipped at the clock inputs of the PHY and the CPU, and will give a good clock source. The harmonic noise will be minimised due to the LC filter.

[A] Thanks for your recommendation. I will try to use notch filter.

If you use the ICPLUS IP101A PHY, which has an own pin for 50 MHz clock out, you do not need an extra XTAL oscillator, only a XTAL.

You might also do a redesign of your PCB and route the clock line on an inner layer, guarded with GND lines left/right.

[A] Thank you for your comment. We are planning to change Ethernet Transceiver to LAN8720 which can use a crystal and has a 50MHz clock output pin.   

Thanks!

Best Regards!

If you use a LAN8720, you will not be able to use a filter in the clock line, because the PHY RMII timing is relative to the clock output, and the filter will add delay to the clock, violating the setup/hold timings on the RMII interface.

The IP101A has 2 clock lines: one clock output, and one clock input. The RMII timing is relative to the clock input, so you might add a filter to the clock output.

regards

Wolfgang

Hi, Wolfgang,

Would you like to introduce some actual product for validation?   we would like to buy several products which used LAN8720 solution for ethernet application. we hope to do the actual measurement for harmonic noise before changing PCBA, it will rise our confidence. thanks a lot.

Best regards,

Zhang Hua

With regard to the LAN8720...please ensure that you complete a RMII interface timing simulation before committing this solution to PCB as the "clock out mode" timing of this PHY+AM35xx is very tight.

Hello DK,

       We are using LAN8700 in our project board  on current.The LAN8720 in develop board by MISTRAL.

       But this problem have found those two boards and LAN interfece works well on those two board.

       And the RMII interface drivers provide by BSP in linux kernel. So i don't know how to do can "complete a RMII interface timing simulation"? can you tell me some steps for that?

       Thanks a lot!

       Best Regards!

       Peter Liu