About the CKE LOW TIME ( time from reset going high to CKE going high on the DDR3) required by JEDEC

 Please check your DDR initialization in u-boot and check if the following is being done. If not, please perform the steps below and see if it helps.

 Initialize SDRAM_REF_CTRL with reset delay value before writing to SDRAM_CONFIG (DDR3 only)

The value in SDRAM _REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value of 0x3100 before writing to SDRAM_CONFIG (which initiates a DDR initialization. During first DDR initialization, the sequence should be:

• Configure all other EMIF registers
• Write SDRAM_REF_CTRL = 0x3100
• Write SDRAM_CONFIG with appropriate value
• Write SDRAM_REF_CTRL with refresh rate value for normal operation

The value of 0x3100 is derived from the following formula:

(16*SDRAM_REF_CTRL)/400MHz > 500us

Note this value can change based on DDR frequency supported and is only needed for DDR3.