maximum support of NAND Flash in AM335X with Boot

alpesh mandani

Intellectual 690 points

HI,

How much maximum NAND flash size and supported on AM335x with 8 bit GPMC interface.

For Boot up process Which type NAND flash support in AM335X with SLC or MLC.

We are planing to use 64Gb NAND flash with 8bit in our product.

thanks.

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi Alpesh,

There is no size restriction for NAND flash size, because NAND resembles a block device - commands, addresses and data are all transferred over the same interface (8-bit in your case). Please check section 26.1.7.4 in the AM335x Technical Reference Manual Rev. K for NAND flash boot requirements.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

Hi Biser,

We are confuse for NAND flash boot requirement in device ID selection base on Table 26-14. Supported NAND Devices in Rev K.

In this table only Two device ID support for boot process with 8 bit X 64Gb NAND Flash. like DE and AE only .

Please let us know any other device Id support for boot process with 64Gb NAND with 8 bit width.

Thanks
Regards,
Alpesh

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

If your NAND is ONFI compatible it will be supported.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

HI Biser,

I have select Below part from micron with 64Gb MLC nand flash.
Part Number# MT29F64G08CBAAA
But in this part, Device ID and 4th data byte are not match with NAND boot requirement in Table 26-14. Supported NAND Devices and Table 26-15. 4th NAND ID Data Byte in TRM Rev :K.

Please let us know this part are support boot process.

Thanks

Regards,
Alpesh

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

This part is ONFI compliant. The problem here is the very large page size (8192 + 448 bytes) which may require a stronger ECC mechanism than the AM335X can support. Maximum supported is BCH16.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

HI Biser,

Thanks for your support.

Can you provide me any recommended 64Gb part number with support Boot process?

I have try to find part number for NAND flash boot requirement but not success.

Please help for part selection.

Thanks.
Regards,
Alpesh

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

Sorry, I cannot do this. TI does not manufacture NAND memories. There are no recommendations, other than those listed in the AM335X TRM section mentioned above.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

Hi biser,
I need DE and AE device ID part number as use When Processes test in TI lab. as per TRM section only two Device ID support and base on this TI have use any other company 64Gb NAND Flash part for Boot performance test.

Please if possible then give me your feed back base on above comment.

Also let us know which type ECC mechanism/change required for above part(# MT29F64G08CBAAA) of Micron MLC NAND Flash to support AM335X

Thanks.

Regards,
Alpesh

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

Table 26-14 is used by the ROM code only if the NAND part is not ONFI compliant. Please read from the beginning of "Device Detection and Parameters" on page 4923. There is no recommended NAND device list available. I would suggest that you look for devices with page size of 2048 or 4096 bytes and additional spare area.

For ECC support check this wiki: https://processors.wiki.ti.com/index.php/Linux_Core_NAND_User%27s_Guide#ECC_schemes_support

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

Hi Biser,
Thanks for your support.
As above comment,Table 26-14 only for non ONFI device.
so we will not need to check device ID for above selected part (MT29F64G08CBAAA) but we need to change only page size (2048/4096)..right?

Regards,
Alpesh

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

Yes, try finding a device that is ONFI compliant and with page size of 2048/4096. If in doubt post here, we'll check your selection and confirm.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

Hi Biser,

Please see below selecting part for 64Gb NAND flash with 4096 Page size and ONFI compliant

Part # MT29F64G08CFABA
Part # MT29F64G08CFACA

above both part are dual die packages so in this part two CE and R/B# signal.

Please let us know this device support with AM335X with boot up.

Thanks,

Regards,
Alpesh

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

Yes, this will be supported, but you will have to use 2 chip selects and you will have 2 logical devices. You must tie the first chip select to GPMC_CS0 (to boot from this logical device). The 2 R/B signals can be wire-OR tied because they are open drain. They must be connected to GPMC_WAIT0 with an external pullup resistor.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

Hi Biser,

Thanks for your support.

As per my understanding we need to connect 2 chip select in different two GPMC port ,one in GPMC_CS0 and other in GPMC_CS1 and 2 R/B Pin directly connect with only one GPMC_WAIT0 with external pull up resistor ....right?.

No need to Connect Two R/B signal with different GPMC_WAIT , GPMC WAIT are common for both R/B signal.

Please let us know meaning of 2 R/B signals wire-OR tied and sorry for that.

Thanks.

Regards,
Alpesh

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

Yes, your understanding is correct. Wire-OR means you can simply connect the two R/B signals and tie them to GPMC_WAIT0, with an external pullup resistor. It's important you use GPMC_WAIT0 and not GPMC_WAIT1, otherwise you will not be able to boot.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

Hi Biser,
Thanks for your support.

Can you tell me why Wire ORing required for ready/busy signal for Boot up process?

Thanks

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

Wire OR is not a boot requirement, but the NAND you boot from must have its R/B signal connected to GPMC_WAIT0 or you will not be able to boot from it.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

Hi Biser,

Thanks for your support.
We are confuse for Chip selection for NAND Boot mode. as per my understanding first chip select must be connect with GPMC_CS0, but second chip select connect to any other GPMC_CSn or need any dedicated GPMC_CSn for NAND Boot?

Please let us know your feedback.

Thanks,
Regards,
Alpesh

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

NAND boot is supported only on GPMC_CS0. Please check section 26.1.7.4.2.2 in the AM335X TRM Rev. K.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

Hi Biser,
Thanks for your support.

As per above discuss we have select micron NAND flash part # MT29F64G08CFACA with Two die , so we need to support for NAND with Boot mode with first chip select must be connect to GPMC_CS0.

But which GPMC_CS pin use for second chip select pin connection ?

Thanks
Regards
Alpesh

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

Whichever you like, there are no restrictions.

0 alpesh mandani over 10 years ago in reply to alpesh mandani

Intellectual 690 points

Hi Biser,

Please give me your valuable feedback on above thread.

Regards,
Alpesh

0 alpesh mandani over 10 years ago in reply to alpesh mandani

Intellectual 690 points

Hi Biser,
As per my understanding we have use GPMC_CS0 for first Chip select and for second chip select connect to any other GPMC_CSn pins and 2 R/B signal are Oring.... and its work without any issues in NAND Boot process....right?

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

Correct.

0 alpesh mandani over 10 years ago in reply to alpesh mandani

Intellectual 690 points

Hi biser,
Thank for your support.
Please can you explain me how to work two logical device of NAND flash booting process and after booting for storage application if two chip select different pin assignment and 2R/B signal tie to Oring?
We have a some confusion for ready busy signal response and assignment for two logical device work at same time because of 2R/B signals together and both device chip select are different.

Please give me your feedback.
Thanks

0 Biser Gatchev-XID over 10 years ago in reply to alpesh mandani

TI__Guru**** 393215 points

The R/B signal is currently not used by the Linux NAND driver. It's necessary only for booting.

0 alpesh mandani over 10 years ago in reply to Biser Gatchev-XID

Intellectual 690 points

Hi Biser,

Thanks for your support.

Regards,

Alpesh

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maximum support of NAND Flash in AM335X with Boot