AM335x DDR3 DQS timing

takeshi matsuzaki

Expert 2030 points

Hello

My customer fails DDR3 compliance test with AM335x.

They have already set DDR3 register with using this wiki
processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips
processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling
and software leveling, but it fails.

They want to change DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 timing to pass the DDR3 compliance.

These registers afect the DQS timig ?

DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0
DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0
DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0
DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0

DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0
DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0

Regards,
Takeshi Matsuzaki

over 11 years ago

0 Biser Gatchev-XID over 11 years ago

TI__Guru**** 393215 points

Hi Matsuzaki-san,

I will ask the DDR experts about this.

0 takeshi matsuzaki over 11 years ago in reply to Biser Gatchev-XID

Expert 2030 points

Hello,Any informations ?Regards,Takeshi Matsuzaki

0 Biser Gatchev-XID over 11 years ago in reply to takeshi matsuzaki

TI__Guru**** 393215 points

Nothing so far. Feedback will be posted here when available. Please note that it was Easter holiday this weekend in the USA.

0 sivak over 11 years ago in reply to Biser Gatchev-XID

TI__Genius 9655 points

Takeshi-san

Can you help provide more information on this -
1) What is the specific parameter that failed the JEDEC compliance test?
2) Just changing DQS in isolation will impact the READ/WRITE timings.
3) Was SW leveling performed? Can you help share the results?
4) Did you try with invert_clkout=1?

Regards, Siva

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AM335x DDR3 DQS timing